Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-03-08
2011-03-08
Stark, Jarrett J (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S108000, C257S686000
Reexamination Certificate
active
07901985
ABSTRACT:
A manufacturing method of a package on package with a cavity. The method can include forming a first upper substrate cavity in one side of an upper substrate; mounting an upper semiconductor chip on the other side of the upper substrate; forming a lower substrate cavity in one side of a lower substrate; mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
REFERENCES:
patent: 4288841 (1981-09-01), Gogal
patent: 5327325 (1994-07-01), Nicewarner, Jr.
patent: 5646828 (1997-07-01), Degani et al.
patent: 6180881 (2001-01-01), Isaak
patent: 6313522 (2001-11-01), Akram et al.
patent: 6542393 (2003-04-01), Chu et al.
patent: 7528474 (2009-05-01), Lee
patent: 7727799 (2010-06-01), Lin
patent: 2007/0216008 (2007-09-01), Gerber
patent: 2009/0115049 (2009-05-01), Shiraishi et al.
patent: 2010/0240175 (2010-09-01), Hong
patent: 1993-0017160 (1993-08-01), None
patent: 10-0259450 (2000-03-01), None
Korean Patent Office Action, mailed Oct. 26, 2006 and issued in Korean Patent Application No. 10-206-0014917 cited Korean Patent Publication Nos. 1993-0017160 (Reference AG) and 10-0259450 (Reference AH).
U.S. Appl. No. 11/706,223, filed Feb. 15, 2007, Jee-Soo Mok et al., Samsung Electro-Mechanics Co., Ltd.
Korean Office Action, dated Oct. 26, 2007, issued in priority Korean Application No. 10-2006-0014917.
Chinese Patent Office Action, mailed Mar. 21, 2008 and issued in corresponding Chinese Patent Application No. 200710079522.5.
U.S. Patent Office Action, mailed Jun. 25, 2008, issued in corresponding U.S. Appl. No. 11/706,223.
U.S. Patent Office Action, mailed Nov. 6, 2008, issued in corresponding U.S. Appl. No. 11/706,223.
U.S. Patent Notice of Allowance, mailed Jun. 11, 2009, issued in corresponding U.S. Appl. No. 11/706,223.
Mok Jee-Soo
Park Dong-jin
Ryu Chang-Sup
Samsung Electro-Mechanics Co. Ltd.
Stark Jarrett J
Tobergte Nicholas
LandOfFree
Method for manufacturing package on package with cavity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing package on package with cavity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing package on package with cavity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2743894