Method for manufacturing NAND type semiconductor memory device

Details Method for manufacturing NAND type semiconductor memory device Method for manufacturing NAND type semiconductor memory device

1995-05-26

1997-01-14

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 48, 437149, H01L 218246

Patent

active

055939040

ABSTRACT:
A plurality of gate electrodes are formed over a semiconductor substrate of a first conductivity type, and impurities of a second conductivity type are introduced into the substrate with a mask of the gate electrodes, to form source/drain impurity regions. Then, an insulating pattern is formed on the gate electrode and the source/drain impurity regions, and impurities of the second conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a deep base region which is connected to one of the source/drain impurity regions. Also, impurities of the first conductivity type are introduced into the substrate with a mask of the insulating pattern, to form a shallow emitter region.

REFERENCES:
patent: 4914047 (1990-04-01), Seki
patent: 5171705 (1992-12-01), Choy
patent: 5397723 (1995-03-01), Shirota et al.
patent: 5429968 (1995-07-01), Koyama
N. Rovedo etal., "Process Design for Merged Complementary BiCMOS", IEDM Technical Digest, 1990, pp. 485-488.

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