Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2008-11-14
2010-11-02
Stark, Jarrett J (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S003000, C257SE21214
Reexamination Certificate
active
07825027
ABSTRACT:
A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes.
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Higuchi Toshihiko
Noda Takafumi
Harness & Dickey & Pierce P.L.C.
Seiko Epson Corporation
Stark Jarrett J
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