Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2007-08-02
2008-12-02
Tsai, H. Jey (Department: 2895)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S312000, C438S340000
Reexamination Certificate
active
07459368
ABSTRACT:
Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor region above the opening, is applied over the etch stop layer and over the opening. Before etching of the semiconductor material, a masking layer is applied above the collector semiconductor region to the semiconductor material, which protects the collector semiconductor region from the etching. Afterwards the semiconductor material is etched to the depth of the etch stop layer, the etch stop layer acting as an etch stop such that reaching an interface between the semiconductor material and the etch stop layer is detected during the etching and the etching is stopped depending on the detection.
REFERENCES:
patent: 5385861 (1995-01-01), Bashir et al.
patent: 5403757 (1995-04-01), Suzuki
patent: 5912678 (1999-06-01), Saxena et al.
patent: 2004/0222486 (2004-11-01), Ellis-Monaghan et al.
patent: 19758339 (1999-06-01), None
patent: 10152089 (2003-05-01), None
patent: 0263756 (1988-04-01), None
patent: 0430279 (1991-06-01), None
patent: 58153349 (1983-09-01), None
patent: 62213258 (1987-09-01), None
patent: WO 02/103776 (2002-12-01), None
Van Huylenbroeck S et al: “Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology” Bipolar BICMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Montreal, Sep. 12, 2004, pp. 229-232.
John P et al: “Elimination of NPN C-E Leakage Yield Loss on SiGe: C HBTBiCMOS Technology through Optimization of Critical Wet Chemical Wafer treatments” 2003 IEEE International Symposium on Semiconductor Manufacturing. Conference Proceedings. (ISSM 2003). San Jose, CA, Sep. 30-Oct. 2, 2003, IEEE International Symposium on Semiconductor Manufacturing, New York, NY : IEEE, US, Sep. 30, 2003, pp. 411-414.
Kempf P et al: “Silicon Germanium BICMOS Technology” GAAS IC Symposium. 24TH. Annual IEEE Gallium Arsenide Intefrated Circuit Symposium. Technical Digest 2002. Monterey, CA, Oct. 20-23, 2002, GAAS IC Symposium—IEEE Gallium Arsenide Integrated Circuit Symposium, New York, NY: IEEE, US, Oct. 20, 2002, pp. 3-6.
Osten H J et al: “Dopant diffusion control by adding carbon into Si and SiGe: principles and device application” Materials Science and Engineering B, Elsevier Sequoia, Lausanne, CH, vol. 87, No. 3, Dec. 19, 2001, pp. 262-270.
Widmann et al., “Large-Scale Integrated Circuit Technology”, Springer Verlag, Second Edition, 1996, pp. 206-210.
Atmel Germany GmbH
Muncy Geissler Olds & Lowe, PLLC
Tsai H. Jey
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