Method for manufacturing integrated circuits complete with high

Details Method for manufacturing integrated circuits complete with high Method for manufacturing integrated circuits complete with high

1995-11-09

1998-01-27

Fourson, George

Fishing, trapping, and vermin destroying

437 89, 437 60, 437 47, H01L 2176

Patent

active

057121842

ABSTRACT:
A method for manufacturing integrated circuits complete with integrated low loss capacitances, inductances, and high Q resistors. Initially a large number of monocrystalline--in their lateral and vertical directions dielectrically insulated--boxes for receiving the active devices of the integrated circuit are generated on a semiconductor substrate wafer with high resistivity. A subset of the completely insulated boxes is to provide for receiving the active devices generated by appropriate bipolar, MOS, or BiCMOS technologies. The other subset is to provide for receiving the passive devices. From these boxes, the monocrystalline semiconductor material is removed completely. In the empty boxes, the walls of which boxes consist of a dielectric, thin film conductor structures are defined by deposition and lithographic processes, eventually forming the passive devices. Due to the layer combination of thin film conductor/dielectric/substrate with high resistivity, the passive devices manufactured in these boxes will be marked by very low losses only, i.e. they are possessed of a high quality (Q).

REFERENCES:
patent: 4161742 (1979-07-01), Kane
patent: 4292730 (1981-10-01), Ports
patent: 4418470 (1983-12-01), Naster et al.
patent: 4819037 (1989-04-01), Sakakibara et al.
patent: 5001075 (1991-03-01), Boland et al.
patent: 5047828 (1991-09-01), Soclof
patent: 5071792 (1991-12-01), VanVonno et al.
patent: 5145795 (1992-09-01), Sanders et al.
patent: 5258318 (1993-11-01), Buti et al.
patent: 5268326 (1993-12-01), Lesk et al.
patent: 5521412 (1996-05-01), Walker et al.
Ohno, Terukazu et al.; "Total-Dose Effects of Gamma-Ray Irradiation on CMOS/SIMOX Devices"; IEEE Circuits and Devices Magazine, Nov. 1987, pp. 21-25.
Tsao, Sylvia; "Porous Silicon Techniques for SOI Structures"; and Barla, Kathy et al.; SOI Technology Using Buried Layers of Oxidized Porous Si; IEEE Circuits and Devices Magazine, Nov. 1987, pp. 3-7, 11-15.

Affiliated with

Also associated with

Rating

Method for manufacturing integrated circuits complete with high does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing integrated circuits complete with high , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing integrated circuits complete with high will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-341802