Method for manufacturing highly-integrated stacked capacitor

Details Method for manufacturing highly-integrated stacked capacitor Method for manufacturing highly-integrated stacked capacitor

1993-08-25

1994-03-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437915, 437982, H01L 2172

Patent

active

052945618

ABSTRACT:
An impurity doped region is formed in a semiconductor substrate, and an insulating layer is formed thereon. A conductive layer is formed and is patterned by a photolithography process Then, a conductive sidewall is formed inside of the conductive layer. The insulating layer is etched with a mask of the conductive sidewall and the conductive layer to create a contact hole leading to the impurity doped region. A capacitor lower electrode layer is deposited within the contact hole. Thus, a capacitor insulating layer and a capacitor upper electrode layer are formed, to obtain a stacked capacitor.

REFERENCES:
patent: 4987092 (1991-01-01), Kobayashi et al.
patent: 5162249 (1992-11-01), Kim
patent: 5238862 (1993-08-01), Blalock et al.

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