Method for manufacturing highly-integrated capacitor

Details Method for manufacturing highly-integrated capacitor Method for manufacturing highly-integrated capacitor

1996-05-10

1997-08-12

Niebling, John

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438964, H01L 2170

Patent

active

056565291

ABSTRACT:
In a method for manufacturing a capacitor, a lower electrode is formed by an amorphous refractory metal silicide layer and its underlying conductive layer, a heating operation is performed upon the amorphous refractory metal silicide layer, so that the amorphous refractory metal silicide layer is converted into a polycrystalline refractory metal layer having an uneven surface.

REFERENCES:
patent: 5466629 (1995-11-01), Mihara et al.
patent: 5470775 (1995-11-01), Nariani
patent: 5554558 (1996-09-01), Hsu et al.
H. Watanabe et al.; "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs"; IEDM 92, (1992), pp. 259-262.
S.P. Sim et al.; "A New Stacked SMVP (Surrounded Micro Villus Patterning) Cell for 256 Mega and 1 Giga bit DRAMs"; International Conference on Solid State Devices and Materials (1993), pp. 886-888.
S. Yu et al.; "The Honeycomb-Shape Capacitor Structure for ULSI DRAM"; IEEE Electron Device Letters, vol. 14, No. 8, Aug. 1993, pp. 369-371.

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