Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2000-12-15
2002-11-26
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S147000, C349S043000
Reexamination Certificate
active
06486934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display device, and in particular to a fringe field switching mode liquid crystal display device including a pixel electrode and a counter electrode of a transparent material which generate a fringe field having homogeneous elements in parallel to a surface of a rear substrate in a liquid crystal cell.
2. Description of the Background Art
A homogeneous alignment mode liquid crystal display device developed by Hitachi company in Japan is an in-plane switching mode liquid crystal display device, and has a better field angle property than a twisted nematic mode liquid crystal display device. However, the homogeneous alignment mode liquid crystal display device has a poor opening ratio and transmissibility. In order to overcome such a disadvantage, there has been suggested a fringe field switching mode liquid crystal display device.
In the fringe field switching mode liquid crystal display device, a counter electrode and a pixel electrode consist of a transparent conductive material on a rear substrate. An interval between the counter electrode and the pixel electrode is larger than an interval between a front substrate and the rear substrate. Accordingly, when a picture voltage is applied between the counter electrode and the pixel electrode, a fringe field is generated in a liquid crystal cell, thereby re-aligning liquid crystal molecules.
A method for manufacturing the fringe field switching mode liquid crystal display device will now be described with reference to FIG.
1
.
An indium tin oxide(ITO) layer is formed at the upper portion of the rear substrate
1
according to a sputtering method, by using Ar gas, O
2
gas and ITO target. The ITO layer is patterned according to a first mask process, thereby forming a counter electrode
2
in a comb or plate shape.
Thereafter, an opaque metal layer for a gate bus line is formed according to the sputtering method at the upper portion of the rear substrate
1
where the counter electrode
2
has been formed. The opaque metal layer for the gate bus line is patterned according to a second mask process, thereby forming a gate bus line
3
, a gate pad and a common electrode line(not shown).
A gate insulating layer
4
, an amorphous silicon layer
5
and a doped amorphous silicon layer
6
are sequentially stacked at the upper portion of the rear substrate
1
where the gate bus line
3
, common electrode line and gate pad have been formed. The amorphous silicon layer
5
and the doped amorphous silicon layer
6
are patterned according to a third mask process, thereby forming a channel and an ohmic contact portion of a thin film transistor.
An ITO layer is formed according to the sputtering method at-the upper portion of the rear substrate
1
where the channel and ohmic contact portion of the thin film transistor have been formed. The ITO layer is patterned according to a fourth mask process, thereby forming a comb-shaped pixel electrode
7
.
Thereafter, the gate insulating layer
4
is removed according to a fifth mask process, thereby opening the gate pad.
An opaque metal layer for a data bus line is formed according to the sputtering method at the upper portion of the rear substrate where the pixel electrode
7
has been formed and the gate pad has been opened. The opaque metal layer for the data bus line is patterned according to a sixth mask process, thereby forming a source electrode
8
a,
a drain electrode
8
b
and a data bus line(not shown). Here, a contact portion of the gate pad is formed at the same time.
At last, a protective layer(not shown) is deposited at the upper portion of the rear substrate
1
where the source and drain electrodes
8
a,
8
b
and the data bus line have been formed. The protective layer is patterned according to a seventh mask process, thereby opening the pixel electrode
7
and the contact portion of the gate pad.
However, the conventional method for manufacturing the fringe field switching mode liquid crystal display device has a disadvantage in that a manufacturing time and cost are increased and a yield is reduced due to many mask processes.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for manufacturing a fringe field switching mode liquid crystal display device which can decrease a number of mask processes.
In order to achieve the above-described object of the present invention, a method for manufacturing a fringe field switching mode liquid crystal display device is applied to a fringe field switching mode liquid crystal display device including a pixel electrode and a counter electrode formed on a rear substrate to generate a fringe field in a liquid crystal cell; a thin film transistor consisting of a gate electrode, a source electrode, a drain electrode and a channel, and applying a picture signal between the pixel electrode and the counter electrode; and a gate pad formed at the edge of the rear substrate. Firstly, a transparent conductive layer for a counter electrode and an opaque metal layer for a gate bus line are sequentially stacked on the surface of the rear substrate. The transparent conductive layer for the counter electrode and the opaque metal layer for the gate bus line are patterned in an identical shape, thereby forming a gate bus line connected to the gate electrode, a counter electrode region for forming the counter electrode, and a gate pad region for forming the gate pad. Thereafter, a gate insulating layer, an amorphous silicon layer and a doped amorphous silicon layer are sequentially stacked on the rear substrate where the gate bus line and the counter electrode region have been formed. The gate insulating layer, the amorphous silicon layer and the doped amorphous silicon layer are patterned in an identical shape, thereby forming an active region overlapped with the whole region of the gate bus line. The opaque metal layer for the gate bus line in the counter electrode region and gate pad region is removed, thereby forming the counter electrode and the gate pad. An electrode insulating layer is deposited on the rear substrate where the active region, counter electrode and gate pad have been formed. The electrode insulating layer is patterned, thereby opening a part of the active region and the gate pad. A transparent conductive layer for a pixel electrode and an opaque metal layer for a data bus line are deposited on the rear substrate where the active region and gate pad region have been opened. The transparent conductive layer for the pixel electrode and the opaque metal layer for the data bus line are patterned in an identical shape, thereby forming a data bus line crossing the gate bus line, a source electrode and a drain electrode respectively electrically connected to the active region, the channel of the thin film transistor being positioned therebetween, a pixel electrode region for forming the pixel electrode to be overlapped with the counter electrode, and a contact portion of the gate pad. Thereafter, a protective layer is deposited on the rear substrate where the data bus line, source electrode, drain electrode, pixel electrode region and gate pad have been formed. The deposited protective film is patterned, thereby opening the pixel electrode region and the contact portion of the gate pad. Thereafter, the opaque metal layer for the data bus line in the opened pixel electrode region is removed, thereby forming the pixel electrode.
REFERENCES:
patent: 6172728 (2001-01-01), Hiraishi
patent: 6335770 (2002-01-01), Komatsu
patent: 6362858 (2002-03-01), Jeon et al.
Kwon Young Tae
Park Seong Yik
Yun Suk Shin
Hyundai Display Technology Inc.
Ladas & Parry
Rude Timothy L
Ton Toan
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