Method for manufacturing fine-structured stacked connection laye

Details Method for manufacturing fine-structured stacked connection laye Method for manufacturing fine-structured stacked connection laye

1993-11-26

1995-04-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437194, 437195, H01L 2144, H01L 2148

Patent

active

054078628

ABSTRACT:
A first insulating layer is formed on a semiconductor substrate. A lower metal layer and a upper metal layer are sequentially formed on the first insulating layer, and also, a second insulating layer is formed thereon. Then, a photoresist pattern is formed, and the second insulating layer and the upper metal layer are etched with a mask of the patterned photoresist layer. Then, the patterned photoresist layer is removed, and a sidewall insulating layer is formed on a side of the upper metal layer. Finally, the lower metal layer is etched with a mask of the second insulating layer and the sidewall insulating layer.

REFERENCES:
patent: 5100838 (1992-03-01), Dennison
patent: 5262352 (1993-11-01), Woo et al.
M. Kobayashi et al., "Metal Etching Technology", Monthly Semiconductor World, Oct. 1991, pp. 116-119.

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