Method for manufacturing element isolation structural section

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C257SE21546

Reexamination Certificate

active

11453993

ABSTRACT:
A plurality of element forming regions and an element isolation structural section forming region which separates the plurality of element forming regions from one another, are set to a substrate. A first thermal oxide film is formed. An HfSiON film is formed. Heating processing is done. A silicon nitride film is formed. A trench is formed which extends from an upper surface of the substrate, corresponding to the element isolation structural section forming region to within the substrate. A trench oxide film is formed. A precursor embedded oxide film is formed. The precursor embedded oxide film is removed as a height lower than the upper surface of the silicon nitride film. Then, the silicon nitride film is removed. The HfSiON film and the first thermal oxide film are removed. A second thermal oxide film is formed on an exposed surface of the substrate from which the HfSiON film and the first thermal oxide film are removed. An embedded portion is formed as the same height as that of the exposed surface of the substrate.

REFERENCES:
patent: 6717231 (2004-04-01), Kim et al.
patent: 6933238 (2005-08-01), Asakawa
patent: 2006/0073671 (2006-04-01), Iinuma
patent: 2006/0183296 (2006-08-01), Yoo et al.
patent: 2006/0205173 (2006-09-01), Song et al.
patent: 2000-022153 (2000-01-01), None

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