Semiconductor device manufacturing: process – Gettering of substrate
Reexamination Certificate
2000-04-17
2002-09-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Gettering of substrate
C438S528000, C438S445000
Reexamination Certificate
active
06451672
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method for manufacturing monolithically integrated electronic devices in semiconductor substrates provided with gettering sites, and to a wafer of a semiconductor material for the manufacturing of electronic devices according to the above method.
BACKGROUND OF THE INVENTION
This technical field specifically requires that metal contaminants be removed from substrates of integrated circuits. Unfortunately, metal contaminants are normally found in semiconductor substrates and their presence can seriously affect the performance of integrated circuits formed in such substrates.
The presence of metal impurities is often a source of trouble and malfunction in electronic semiconductor devices. Accordingly, the possibility of clearing the silicon of all metal impurities has been the subject of intensive study and research work in recent years.
To fill this demand, gettering techniques are used which allow electronic devices that are monolithically integrated in a semiconductor to be provided with so-called gettering sites for trapping any metal contaminants present in the semiconductor.
Such gettering sites are created near the end of the processing steps that lead to the formation of integrated circuits. For this purpose, the front side of the semiconductor wafer is coated with a protective layer, and the back side of the wafer is cleaned and subjected to a step of POC
13
deposition or phosphorus (P) ion implantation, in order to produce certain extended faults in the semiconductor substrate.
These extended faults in the crystalline structure of the semiconductor effectively function as gettering sites capable of attracting and segregating metal atom impurities, as further described hereinafter.
This gettering technique involves, however, some manufacturing problems, since it is applied at the end of the manufacturing process and can impair the quality of circuits previously formed in the semiconductor wafer. In addition, the gettering efficiency of faults formed in this way is not particularly high.
More recently, the prior art proposed that microvoids be produced in the semiconductor substrate by subjecting it to a step of implanting light ions of a noble gas, such as helium (He). These ions are highly permeable through silicon and implanted at a high concentration (>5×10
15
atoms/cm
2
) and low energy, such that gas bubbles are produced within the crystalline structure.
The energy level at which the implanting step is carried out represents no particular limitation to a successful implantation. In fact, a few keV to tens of MeV may be used. However, as the implanting energy increases, the minimum dosage for bubble formation also increases.
Optimum conditions for forming bubbles through the silicon are achieved at an implanting energy in the 50 to 300 keV range, as described in an article, “Gettering of metals by voids in silicon”, Journal of Applied Physics, No. 78(6), Sep. 15, 1995.
At energy levels below that, there occur phenomena of the semiconductor surface exploding, while at higher energy levels, such high implantation dosages must be used that the processing step ceases to be cost-efficient.
A thermal treatment applied after the implanting step, at a temperature above 700° C., allows the gas to diffuse through the crystalline structure up to the semiconductor surface, where it will evaporate.
In evaporating, the gas leaves microvoids in the crystalline structure whose average diameter increases as the process temperature is increased. Also, these microvoids are confined locally within the projection regions of the implanted ions.
It has been found that the microvoids have a fault that is thermally stable in silicon. This means that, even subsequent to thermal treatments applied after the bubble forming, they do not evolve into crystallographic faults of another nature. This phenomenon is described in an article, “Efficiency and thermal stability of Pt gettering in crystalline Si”, Journal of Applied Physics, No. 80(8), Oct. 15, 1996.
On the surfaces of the microvoids formed as described above, there appear silicon atoms having unsaturated bonds and being highly reactive to impurities, in particular to such metal impurities as copper (Cu), platinum (Pt), or iron (Fe).
An example of a different application of microvoids produced by implanting He ions is known as a life span controlling technique and described in European Patent Application No. 0694960 by Co.Ri.M.Me., and herein incorporated by reference, which discloses a process for producing microvoids from helium bubbles implanted beneath the active areas of an integrated electronic device.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a process for manufacturing electronic devices which are integrated monolithically in a semiconductor and have self-gettering features, that is, an inherent capability of trapping out metal contaminants from the semiconductor. Specifically, one embodiment of the invention uses steps of implanting noble gas ions into the semiconductor substrate, followed by a thermal treatment to create bubbles through the substrate by evaporation of said gas.
These embodiments are able to provide a semiconductor substrate with self-gettering properties by acting on the back side of a semiconductor wafer incorporating this substrate before the wafer is subjected to the process steps that result in the integrated circuits being formed. The back surface of the semiconductor wafer is pre-treated for the formation of gettering sites, prior to the wafer front polishing step.
Embodiments of the invention include methods for implanting noble gas ions into the back surface of the substrate, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas, prior to starting the manufacturing process for electronic devices.
These methods produce a wafer of a semiconductor material for manufacturing electronic devices or circuits integrated in a semiconductor substrate which is bounded by a front surface of the wafer and an opposed back surface thereof. The back surface of the wafer includes gettering sites which have been formed by implanting ions of a noble gas, followed by thermal treatment to form bubbles through the semiconductor by evaporation of the gas.
The features and advantages of the methods according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
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Raineri et al., “Gettering of Metals by Voids in Silicon,”Journal of Applied Physics78(6):3727-3735, Sep. 15, 1995.
Petersen et al., “Gettering of Transition Metals by Cavities in Silicon Formed by Helium Io Implantation,”Nuclear Instruments and Methods in Physics Research,Section B, 127-128: 301-306, May 1, 1997.
Zhang et al., “Gettering of Cu by Microcavities in Bonded/Ion-Cut Silicon-on-Insulator and Separation by Implantation of Oxygen,”Journal of Applied Physics86(8):4214-4219, Oct. 15, 1999.
Raineri et al., “Lifetime Control in Silicon Devices by Voids Induced by He ion Implantation”,Journal of Applied. Physics79 (12), pp. 9012-9016, Jun. 15, 1996.
Battaglia et al., “Gettering of Metals by Voids in Silicon Devices”, inproceedings 24th European Solid State Device Research conference (ESSDERC 94)— Edinburgh 11 — 15 Sep. 1994, edited by C. Hill and P. Ashburn, (Editions Frontieres, Gif-sur-Yvette, 1994), pp. 403-406.
Raineri et al., “Gettering of Metals by He Induced Voids in Silicon”,Nuclear Instruments and Methods in Physics Research B 96, pp. 249-252, 1995.
Raineri et al., “Gettering of Metals by Voids in Silicon”,J. Appl. Phys.78 (6), pp. 3727-3735, Sep. 15, 1995.
Caruso Davide
Raineri Vito
Saggio Mario
Stagnitti Umberto
Iannucci Robert
Jorgenson Lisa
Le Dung Ang
Nelms David
Seed IP Law Group PLLC
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