Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2001-05-18
2002-07-16
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S501000, C438S218000, C438S219000, C438S294000, C438S353000, C438S400000
Reexamination Certificate
active
06420769
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for manufacturing electronic devices having high voltage (HV) transistors and low voltage (LV) transistors with salicided junctions.
BACKGROUND OF THE INVENTION
In advanced processes (gate lengths of 0.35 &mgr;m or less), the need has recently arisen to integrate HV transistors in high-speed devices which use the technique of saliciding the diffusions. As is known, this technique is based on the use of a layer of self-aligned silicide (“salicide”), which reduces the resistivity of the junctions. The salicide layer (typically of titanium, but also cobalt or another transition metal) is obtained by depositing a titanium layer on the entire surface of the device, and performing a heat treatment that makes the titanium react with the silicon, which is left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example that deposited on oxide regions), is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have in parallel a layer of silicide with low resistivity (approximately 3-4 &OHgr;/square), which makes it possible to reduce the resistance in series at the transistors. The salicide technique is described for example in the article “Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semi-conductor technologies” by R. A. Haken, in J. Vac. Sci. Technol. B, vol. 3, No. 6, November/December 1985.
The HV transistors are formed without intensive implanting doping ionic species, to obtain lightly doped junctions, which thus have a high breakdown voltage. The saliciding process is difficult if the silicon beneath is lightly doped, and this means that it is necessary to avoid saliciding the junctions of the HV transistors.
Process flows are thus being designed which permit integration of HV transistors and LV transistors with saliciding; however this integration is made difficult by the fact that these components have different characteristics, and require different process steps.
SUMMARY OF THE INVENTION
The invention described herein provides a method for manufacturing high-speed HV transistors and LV transistors that is simple and has the lowest possible costs.
According to the invention, a method is provided for manufacturing electronic devices comprising high-speed HV transistors and LV transistors with salicided junctions.
Hereinafter, a production process will be described, aimed to produce EEPROM memory cells, besides LV and HV transistors; however, the invention relates in general to the production of LV and HV transistors, irrespective of the memory cells and the specific process described.
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Dalla Libera Giovanna
Galbiati Nadia
Patelmo Matteo
Vajana Bruno
Flynn Nathan
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
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