Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-02-14
2006-02-14
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S696000, C438S712000, C438S713000
Reexamination Certificate
active
06998348
ABSTRACT:
A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.
REFERENCES:
patent: 4589952 (1986-05-01), Behringer et al.
patent: 4814041 (1989-03-01), Auda
patent: 5525542 (1996-06-01), Maniar et al.
patent: 5716494 (1998-02-01), Imai et al.
patent: 5910453 (1999-06-01), Gupta et al.
patent: 5994228 (1999-11-01), Jeng et al.
patent: 6028001 (2000-02-01), Shin
patent: 6040247 (2000-03-01), Chung
patent: 6235214 (2001-05-01), Deshmukh et al.
patent: 6326307 (2001-12-01), Lindley et al.
patent: 6326312 (2001-12-01), Kim
patent: 6329109 (2001-12-01), Figura et al.
patent: 6329292 (2001-12-01), Hung et al.
patent: 6524875 (2003-02-01), Figura et al.
patent: 6620575 (2003-09-01), Kim et al.
patent: 6693038 (2004-02-01), Shen
patent: 6699792 (2004-03-01), Wang et al.
patent: 6716763 (2004-04-01), Li et al.
patent: 2001/0024769 (2001-09-01), Donoghue et al.
patent: 2002/0175414 (2002-11-01), Teh et al.
patent: 0 871 213 (1998-10-01), None
patent: 1 041 613 (2000-10-01), None
patent: WO 01/31697 (2001-05-01), None
M. Pons et al., Jpn. J. Appl. Phys. part 1, 33 (2), 991, 1994.
O. Joubert et al. SPIE, vol. 1803, 130 (1992).
Moreau, Wayne, Semiconductor Lithography, Plenum, 1988, pp. 631-638, 690-693, 715-717, 724-738.
Alba Simone
Ciovacco Francesco
Colombo Roberto
Savardi Chiara
de Guzman Dennis M.
Ghyka Alexander
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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