Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2002-07-12
2004-07-20
Nguyen, Van Thu (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S106000, C438S107000
Reexamination Certificate
active
06764881
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to electro-ceramic components such as MEMS arrays and methods for fabricating electro ceramic components with high density interconnects and that maintain relative internal alignment. Components constructed according to the invention are MEMS arrays or other micromachined elements.
Conventional MEMS array structures comprise Silicon on Insulator (SOI) array structures in which is fabricated an integrated electrode array. One of the problems encountered is lack of scalability due to connector fan out limitations. A solution is needed. One possible solution might be found in array structures in development of XROS, Inc. of Sunnyvale, Calif.
XROS, Inc., in WIPO Publication WO 00013210 published Mar. 9, 2000, has disclosed elements of a hybrid structure for a MEMS array in which an SOI mirror or micromachined structure without electrodes is bonded to an unspecified insulating substrate on which is provided electrostatic electrodes for actuation of the mirror structure. The disclosure is silent about scaling of devices or about other provisions affecting operation in a thermally-stressed environment.
It has been discovered that the thermal coefficient of expansion mismatch between different components of an electro ceramic structure causes the structure to fall out of alignment, compromising the structure and the uniformity of operation of electrostatic actuators.
What is needed is a micromachined structure that can be scaled and be reliably manufactured and reliably operate over a range of temperature conditions.
SUMMARY OF THE INVENTION
According to the invention, an array apparatus has a micromachined SOI structure, such as a MEMS array, mounted directly on a class of substrate, such as low temperature co-fired ceramic, in which is embedded electrostatic electrodes disposed in alignment with the individual MEMS elements, where the electrostatic electrodes are configured for substantial fanout and the mounting allows for disparate expansion without degradation of performance. In a specific embodiment in order to compensate for differences in thermal-expansion characteristics between SOI and ceramic, a flexible mounting is effected by means of posts, bridges and/or mechanical elements which allow uneven expansion in x and y while maintaining z-axis stability.
Methods according to the invention include fabrication steps wherein electrodes are fabricated to a post-fired ceramic substrate and coupled via traces through the ceramic substrate to driver modules.
The invention will be better understood by reference to the following detailed description in connection with the accompanying illustrations.
REFERENCES:
patent: 5962949 (1999-10-01), Dhuler et al.
patent: 6124663 (2000-09-01), Haake et al.
patent: 2003/0169962 (2003-09-01), Rajan et al.
Bogatin Eric L.
Staker Bryan P.
Teeter, Jr. Douglas L.
Glimmerglass Networks, Inc.
Nguyen Van Thu
Smith Brad
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