Method for manufacturing E.sup.2 PROM

Details Method for manufacturing E.sup.2 PROM Method for manufacturing E.sup.2 PROM

1985-04-09

1986-09-16

Morgenstern, Norman

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 88, 148DIG109, H01L 2927

Patent

active

046122125

ABSTRACT:
An erase gate is formed for erasing data from a floating gate in a semiconductor memory device having the floating gate and a control gate.
Furthermore, in order to achieve electrical insulation between the erase gate and the control gate, an insulating film formed between the erase gate and the control gate is made thicker than an insulating film formed between the floating gate and the erase gate.

REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
1980 IEEE International Solid-State Circuit Conference 152 (Feb. 1980), A 16 Kb Electrically Erasable Nonvolatile Memory.
Kupec et al., Triple Level Poly-Silicon E.sup.2 PROM with Single Transistor per Bit, 1980, IEEE.

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