Method for manufacturing contact hole in semiconductor device

Details Method for manufacturing contact hole in semiconductor device Method for manufacturing contact hole in semiconductor device

2000-12-26

2002-10-22

Powell, William A. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C216S038000, C216S079000, C216S088000, C438S692000, C438S734000, C438S743000

Reexamination Certificate

active

06468920

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for manufacturing a contact hole in the semiconductor device by applying three etching steps.
DESCRIPTION OF THE PRIOR ART
Referring to
FIGS. 1A
to
1
D, there are provided cross sectional views setting forth a conventional method for manufacturing a contact hole using a self align contact (SAC) in a semiconductor device.
The manufacturing steps begin with the preparation of an active matrix provided with a semiconductor substrate
112
, word lines
114
formed on the semiconductor substrate
112
and masks
116
formed on top of the word lines
114
. An etching barrier layer
118
is then formed on the masks
116
and the semiconductor substrate
112
. Thereafter, an interlayer insulating layer
120
is formed over the etching barrier layer
118
and then a top surface of the interlayer insulating layer
120
is flattened by using a chemical mechanical polishing (CMP). Subsequently, a photoresist layer is formed on top of the interlayer insulating layer
120
and patterned into a predetermined configuration, thereby obtaining a patterned photoresist layer
122
as shown in FIG.
1
A.
In a next step as shown in
FIG. 1B
, a first etching step is carried out under conditions of low polymerization, thereby etching upper sides of a contact hole
125
with vertical profiles. While the first etching step is carried out, the polymer
124
is accumulated on the sides of the contact hole.
In an ensuing step, shown in
FIG. 1C
, a second etching step is carried out under conditions of high polymerization in order to protect the etching barrier layer
118
from etching damage until the etching barrier layer
118
in a bottom portion of the contact hole is exposed. While the second etching step is carried out, more and more polymer
124
accumulates on the sides of the contact hole owing to the narrow space between the word lines. Therefore, a thickness of the etching barrier layer
118
in the bottom portion of the contact hole is decreased gradually by etching attack because the polymer is accumulated on the sides. As the second etching step progresses further as shown in
FIG. 1D
, the polymer layers on each side of the contact hole eventually stick to each other so that this may serve as an etch stop, whereby the etching step is not performed any longer.
Therefore, the conventional method for manufacturing the contract hole using SAC in the semiconductor device has disadvantages in that the etching barrier layer may be eroded and, further, the etching process cannot be carried out effectively due to sticking of the polymer on the sides of the contact hole.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a contact hole in a semiconductor device by applying three etching steps, thereby protecting an etching barrier layer from etching damage in the contact hole.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a contact hole in a semiconductor device, the method comprising the steps of a) preparing an active matrix provided with a substrate and word lines formed on the substrate; b) forming an etching barrier layer on the word lines and the substrate; c) forming an interlayer insulating layer on the etching barrier layer; d) forming a photoresist pattern on the interlayer insulating layer for defining a contact hole; e) etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer on the word lines is exposed; f) etching the interlayer insulating layer under conditions of high polymerization; and g) etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer in a bottom of the contact hole is exposed.


REFERENCES:
patent: 6057243 (2000-05-01), Nagayama
patent: 6150281 (2000-11-01), Kusean
patent: 6329292 (2001-12-01), Hung et al.

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