Method for manufacturing complementary insulated gate field effe

Details Method for manufacturing complementary insulated gate field effe Method for manufacturing complementary insulated gate field effe

1977-01-04

1978-09-05

Dost, Gerald A.

Metal working

Method of mechanical manufacture

Assembling or joining

B01J 1700

Patent

active

041108990

ABSTRACT:
Method for manufacturing complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using a silicon nitride layer as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

REFERENCES:
patent: 3913211 (1975-10-01), Seeds et al.
patent: 3983620 (1976-10-01), Spadea
patent: 4027380 (1977-06-01), Deal et al.

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