Method for manufacturing complementary insulated gate field effe

Details Method for manufacturing complementary insulated gate field effe Method for manufacturing complementary insulated gate field effe

1980-08-29

1982-11-16

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148187, H01L 2126

Patent

active

RE0310794

ABSTRACT:
Method for manufacturing semiconductor devices including, e.g., complementary insulated gate field effect transistors of LOCOS (local oxidation of silicon) structure wherein after the formation of a well layer, an impurity having higher doping level than and the same conductivity type as a semiconductor substrate (well layer) is ion implanted at an area in the semiconductor substrate on which a field oxide layer is to be formed using an oxidation-resistive material, e.g. a silicon nitride layer, as a mask, and the semiconductor substrate surface is selectively thermally oxidized using the silicon nitride layer as a mask.

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patent: 3920481 (1975-11-01), Hu
patent: 3983620 (1976-10-01), Spadea
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patent: 4027380 (1977-06-01), Deal et al.
patent: 4047284 (1977-09-01), Spadea
Elektronik-Anzeiger, vol. 6, No. 2, (1974), pp. 27-30.
Microelectronics and Reliability, Pergamon Press, Gt. Britain, vol. 10, 1971, pp. 471 and 472 and 4 pages drawings.
Philips Res. Repts., vol. 26, pp. 166-180, 1971.
IEEE Trans. on Electron Devices, vol. ED-21, No. 6, Jun. 1974, pp. 324-331.
Electronics, vol. 44, pp. 9E and 10E, 1971.
Nikkei Electronics, Japan, Oct. 20, 1975, pp. 26-29.

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