Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1998-04-17
2000-06-27
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
257309, H01L 2120, H01L 218242
Patent
active
060806338
ABSTRACT:
A method for forming the lower electrode of a capacitor comprising the steps of forming a first dielectric layer, a silicon nitride layer and an oxide layer over a substrate. Then, a first conducting layer is formed in an opening making electrical contact with a specified region of the substrate. Next, a first hemispherical grained silicon layer and a second dielectric layer are formed over the first conductive layer. Thereafter, the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer are patterned. Subsequently, a second conductive layer and a second hemispherical grained silicon layer are formed over the whole substrate structure. Next, portions of the second hemispherical grained silicon layer and the second conductive layer lying above the oxide layer and the second dielectric layer are removed. Finally, the second dielectric layer is removed to expose the first hemispherical grained silicon layer. This invention avoids the damaging effects to the first hemispherical grained silicon layer caused by the etching back operation, and prevents the formation of micro-bridges that may erroneously link up adjacent lower electrodes.
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patent: 5933728 (1999-08-01), Sze
patent: 6004846 (1999-12-01), Iee
Chen Anchor
Hong Gary
Huang Hsiu-Wen
Sze Jhy-Jyi
Chaudhuri Olik
Coleman William David
United Semiconductor Corp.
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