Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1999-07-07
2000-04-18
Fourson, George
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438665, 438964, 438255, 430395, H01L 2129
Patent
active
060514760
ABSTRACT:
Disclosed is a method to reduce step difference of a cell region and a peripheral region, and to increase the capacitance. A first intermetal insulating layer, a planarization layer and a second intermetal insulating layer are formed successively on the semiconductor layer including a storage node. A contact hole is formed by etching the first intermetal insulating layer, the planarization layer and the second intermetal insulating layer so that a selected portion of the storage node is exposed. A photoresist pattern in which a wave of saw-teeth shape is formed at sidewalls, is formed on the second intermetal insulating layer so as to fill the contact hole. Spacers are formed at both sidewalls of the photoresist pattern in which the wave of saw-teeth shape is formed. Herein, a wave of saw-teeth shape is formed at inner surfaces of the spacer owing to both sidewalls of the photoresist pattern. The photoresist pattern in which the waves of saw-teeth shape are formed at sidewalls thereof, is removed. A storage node electrode is formed by filling inside of the contact hole and between the spacers with a doped polysilicon layer. Herein, a wave of saw-teeth shape is formed at sidewalls of the storage node electrode owing to the spacer. The spacer and the second intermetal insulating layer are removed, and a dielectric layer and a plate electrode are formed on a surface of the storage node electrode successively thereby forming a capacitor.
REFERENCES:
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5753419 (1998-05-01), Misium
patent: 5837581 (1998-11-01), Cheng
patent: 5858852 (1999-01-01), Aiso et al.
patent: 5981337 (1999-11-01), Chuang
Dongbu Electronics Co. Ltd.
Fourson George
Garcia Joanne A.
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