Method for manufacturing capacitor of semiconductor memory...

Details Method for manufacturing capacitor of semiconductor memory... Method for manufacturing capacitor of semiconductor memory...

2002-03-25

2004-11-09

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06815221

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method for manufacturing a metal-insulator-metal (MIM) capacitor of a semiconductor memory device, which has lower and upper electrodes formed of metal, controlling a thermal budget.
2. Description of the Related Art
As the area of the cross section of cells decreases due to increases in the integration density of semiconductor devices, it becomes more difficult to obtain sufficient capacitance to operate a device. Accordingly, in order to reduce the thickness of dielectric layers in the manufacture of a capacitor necessary to operate a semiconductor memory device of Gigabit capacity or more and increase the effective area of the cross section of the capacitor, various studies have been carried out to form a storage node having a three-dimensional structure. However, it is very difficult to obtain effective capacitance required to operate a semiconductor memory device of Gigabit or higher capacity through the use of a conventional oxide-nitride-oxide (ONO) dielectric layer. Accordingly, a high dielectric layer which is formed of metal oxide, such as Ta
2
O
5
or TaON, and a material having a perovskite structure, such as (Ba, Sr)TiO
3
(BST), SrTiO
3
(STO), BaTiO
3
, Pb(Zr, Ti)O
3
(PZT), or (Pb, La)(Zr, Ti)O
3
(PLZT), has been suggested.
In the manufacture of a capacitor using such a high dielectric layer, it is more preferable to manufacture a MIM capacitor than to manufacture a capacitor employing a polysilicon electrode because the polysilicon electrode needs a low dielectric layer for preventing a dielectric layer from reacting with the polysilicon electrode, and thus there is a limit to which the capacitance can be increased using the polysilicon electrode. On the other hand, in the case of the MIM capacitor using an electrode formed of a metal having a high work function, a barrier layer is formed at the interface between the metal electrode and a dielectric layer and controls leakage current. Accordingly, it is possible to obtain a capacitor having stable electrical characteristics without introducing a low dielectric layer and thus increase capacitance by reducing the thickness of a dielectric layer.
In order to obtain a capacitor having high dielectric characteristics required to operate a semiconductor memory device of Gigabit or higher capacity from a MIM capacitor, a crystallized dielectric layer must be used because a dielectric material, such as Ta
2
O
4
, TaON, BST, or STO, which is generally used to form a dielectric layer of a MIM capacitor, has 2-10 times better dielectric characteristics in a crystallized state than in an amorphous state.
There are methods for crystallizing a dielectric layer including a method for forming a crystalline dielectric layer by depositing and growing a dielectric layer at a high temperature and a method for forming a crystalline dielectric layer by depositing an amorphous dielectric layer and heat-treating the amorphous dielectric layer. However, the method for crystallizing a dielectric layer by depositing the dielectric layer at a high temperature has problems in which a high temperature necessary to sufficiently crystallize the dielectric layer may cause the step coverage characteristics of the dielectric layer to deteriorate and may oxidize a lower electrode and a TiN-based diffusion barrier layer. Accordingly, the method for crystallizing a dielectric layer by depositing an amorphous dielectric layer and heat-treating the amorphous dielectric layer at a high temperature is considered to be more effective to manufacture a MIM capacitor having a crystalline dielectric layer.
According to a conventional method for manufacturing a capacitor, in order to manufacture a MIM capacitor using a method for forming a crystalline dielectric layer through a heat treatment, a lower electrode is formed on a semiconductor substrate, on which underlying structures are already formed. Next, an amorphous dielectric layer is formed on the lower electrode and is heat-treated at a high temperature to be crystallized. Next, an upper electrode is formed on the crystallized dielectric layer. Here, in order to sufficiently crystallize the amorphous dielectric layer, a heat treatment performed at a high temperature is necessary. However, according to this conventional method, the electrodes may cause tensile stress affecting the dielectric layer due to the difference in thermal expansion coefficients between the electrodes and the dielectric layer and a coarsening effect caused by the grain growth of the material of the electrodes as well as the crystallization of the amorphous dielectric layer when heat-treating the amorphous dielectric layer. Accordingly, the physical and electrical characteristics of the MIM capacitor may deteriorate.
In order to solve the above problems, according to another conventional method for manufacturing a MIM capacitor, a lower electrode is heat treated before deposition of a dielectric layer. This method prevents tensile stress from affecting the dielectric layer and prevents the lower electrode from being deformed during the heat treatment of the dielectric layer by allowing the coarsening effect caused by the grain growth of the material of the lower electrode to be produced before depositing the dielectric layer. However, this method has a problem in that discontinuities may be generated at the lower electrode because of coagulation of the lower electrode when heat treating the lower electrode. In addition, even if the lower electrode is heat treated, it is impossible to obtain a stable leakage current value necessary to operate a device. Accordingly, it is difficult to obtain a MIM capacitor having stable electrical characteristics through heat treatment of the lower electrode.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an object of the present invention to provide a method for manufacturing a MIM capacitor of a semiconductor memory device which is capable of preventing a lower electrode from being deformed during heat treating a dielectric layer to be crystallized and thus improving the physical and electrical characteristics of the MIM capacitor.
In accordance with the inveniton, there is provided a method for manufacturing a capacitor of a semiconductor memory device. A lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.
The lower electrode may be formed of a noble metal, conductive noble metal oxide, or conductive metal oxide. Preferably, the lower electrode is formed of Pt, Ru, Ir, PtO, RuO
2
, IrO
2
, SrRuO
3
, BaSrRuO
3
, or LaScCo.
The dielectric layer may be formed of a metal oxide layer or a material layer having a perovskite structure. Preferably, the dielectric layer is a mono layer including a material selected from among Ta
2
O
5
, Al
2
O
3
, TaON, (Ba, Sr)TiO
3
(BST), SrTiO
3
(STO), BaTiO
3
(BTO), PbTiO
3
, Pb(Zr, Ti)O
3
(PZT), SrBi
2
Ta
2
O
9
(SBT), (Pb, La)(Zr, Ti)O
3
, and Bi
4
Ti
3
O
12
or a composite layer of any of the above.
In one embodiment, in heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets are adjusted by controlling any of the temperature, time, and method of their respective heat treatments.
In one embodiment, in heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets are adjusted by controlling the temperature of their respective heat treatments. For example, the dielectric layer can be heat-treated at a first temperature which is higher than the crystallization temperature of the dielectric layer, and the lower electrode can be heat-treated at a second temperature which is hig

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