Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2000-03-31
2001-10-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
C438S239000, C438S396000, C438S710000, C438S241000
Reexamination Certificate
active
06303455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for manufacturing a capacitor.
2. Description of the Related Art
Most capacitors that are formed in conjunction with other semiconductor devices have a pair of polysilicon electrodes. However, the polysilicon electrodes have some drawbacks including the formation of a depletion region whose thickness may vary. A variable thickness often leads to a variation of capacitance and a degradation of device performance. In the current state of technology, variation in depletion layer thickness often results in an even greater variation in capacitance because the inter-layer dielectric layer has become thinner due to miniaturization.
In general, the polysilicon electrodes of a capacitor are doped (for example, using arsenic or phosphorus ions) to increase electrical conductivity. However, when a voltage is applied to the capacitor, electric charges are induced at the junction between the electrode and the inter-layer dielectric layer. The electric charges near the junction cancel most of the effect of produced by the ionic dopants, thereby creating a depletion region.
The depletion region can be regarded as an extension of the inter-layer dielectric layer. The presence of the depletion region, therefore, increases the effective dielectric layer of the capacitor. In general, the charge storage capacity of a capacitor is inversely proportional to the thickness of the inter-layer dielectric layer. In other words, a capacitor having a thin dielectric layer is able to store a greater number of charges. However, the formation of a depletion layer increases the thickness of the dielectric layer, and hence reduces the capacitance of the capacitor. In addition, thickness of the depletion layer varies according to the voltage V applied to the electrodes. This can lead to a variation of the voltage coefficient (1/C(dC/dV)) of a capacitor and hence a de-stabilization of the device. Furthermore, polysilicon has a higher resistivity than other metallic materials. Therefore, polysilicon electrodes often limit the ultimate operating speed and performance of the capacitor.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a capacitor to prevent from generating a depletion region in a top electrode of the capacitor.
In another aspect of the invention, the invention provides a method for manufacturing a capacitor whose performance and frequency are both increased.
The invention provides a method for manufacturing a capacitor. The method includes the following steps. A semiconductor substrate with a peripheral circuit region and a memory cell region is provided. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate apart from the isolation structure. A first polysilicon layer is formed over the gate oxide layer and the isolation structure. A dielectric layer is formed on the first polysilicon layer. A second polysilicon layer is formed on the dielectric layer, and then the second polysilicon layer is patterned to expose a portion of the dielectric layer; the residual second polysilicon layer is above the isolation structure. The exposed dielectric layer is removed to expose a portion of the first polysilicon layer. The first polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime, a polysilicon gate is also formed above the peripheral circuit region. An ion implantation step is performed to form a lightly doped drain region beside the polysilicon gate in the substrate. Spacers are formed on the sidewalls of the polysilicon gate, the residual second polysilicon layer and the bottom electrode, respectively. An ion implantation step is performed to form a source/drain region beside the polysilicon gate in the substrate. A salicidation process is performed to convert the second polysilicon layer entirely into a first silicide layer serving as top electrode of the capacitor, and second silicide layers are formed on the top surface of the polysilicon gate and on the first polysilicon layer, respectively.
In the present invention, the polysilicon layer serves as the bottom electrode of the capacitor, and the silicide layer serves as the top electrode of the capacitor. Since the depletion regions are not to be generated in the metal layer or the silicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, the operating speed and frequency of the capacitor are both increased.
REFERENCES:
patent: 5218511 (1993-06-01), Nariani
patent: 5879981 (1999-03-01), Tanigava
patent: 6015732 (2000-01-01), Williamson et al.
patent: 6147405 (2000-11-01), Hu
patent: 6207995 (2001-03-01), Gardner et al.
Hou Chia-Hsin
Jung Tz-Guei
Ko Joe
Smith Matthew
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
Yevsikov V.
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