Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Subsequent separation into plural bodies
Reexamination Certificate
2002-05-13
2004-04-13
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Subsequent separation into plural bodies
Reexamination Certificate
active
06720238
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a method for manufacturing buried areas on a wafer with an insulating intermediate layer.
2. Description of the Related Technology
Such a method is known from the publication by H. S. Gamble, in Perspectives, Science and Technologies for Novel Silicon on Insulator Devices, 2000. Starting from a wafer which has a complete oxide layer covered by a complete silicide layer, a wafer with a buried suicide layer with an insulating intermediate layer lying underneath that (SOI wafer) is produced by bonding the surface of the silicide layer with the surface of another silicon wafer by means of wafer bonding. After bonding the surfaces, the silicon wafer is thinned by means of further process steps in order to create a silicon layer in which components can be manufactured by further process steps. In order to structure the silicide layer and to create individual silicon areas (boxes) which are isolated from one another, the thinned silicon layer and the underlying silicide layer are etched through by means of a trench process. The trench process stops at the oxide layer lying underneath the silicide layer.
The disadvantage of the method described is that a complete silicide layer has to be buried on an SOI wafer, this silicide layer has to be structured by a trench process, during which, among other things, metallic ions are released, the slightest traces of which impair the properties of the components. This cannot be achieved with reasonable expenditure, particularly if the uppermost silicon layer is somewhat thick. Moreover, undesired parasitic capacitances, which severely impede the use of the SOI wafer for the manufacture of integrated circuits, form on contact surfaces and certain components, such as for example MOS transistors. Moreover, the difference between the coefficient of expansion of the silicide layer and that of the substrate material leads to distortions which, depending upon the temperature process, warp the SOI wafer or create offsets in the active silicon layer. In addition, warped wafers cause substantial expenditure in the lithography modules. Furthermore, it is difficult to manufacture a collector for a vertical, bipolar transistor with this method, as this also requires the silicon wafer used for bonding to be processed before being bonded. A further disadvantage is that tight tolerances on the layer thickness of the uppermost silicon layer can only be maintained with great effort when grinding back the wafer. Moreover, time-consuming cleaning and polishing steps are required after grinding in order to obtain an acceptable surface quality.
AS SOI wafers offer substantial advantages in comparison to conventional silicon substrates for the manufacture of integrated circuits, such as for example the complete suppression of substrate currents and, provided that there are no complete buried metal layers, the lowest parasitic capacitances, wafers with an insulating intermediate layer are increasingly being used as the starting material for the production of integrated circuits in the field of semiconductor technology. Moreover, individual component boxes which are completely isolated from one another can be manufactured on SOI wafers by means of a trench technology, these boxes may lie on a different electrical potential. In order to combine specific component properties on one SOI wafer, one of the objectives of the development in this field is to achieve extremely low connection resistances for specific types of components by means of burying spatially bounded layers, hereinafter referred to as areas, such as for example silicides, whereas very small parasitic capacitances of the insulating intermediate layer are achieved for other types of components.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method with which buried areas can be easily and economically manufactured on a wafer with an insulating intermediate layer.
This object has been achieved according to the invention in a method for fabricating a manufactured multi-layered silicon wafer by bonding together a first silicon wafer and a second silicon wafer.
According to this, the essence of the invention consists of starting with a wafer which has an insulating intermediate layer, and creating areas with at least one changed layer parameter on or within the uppermost silicon layer, and to bury these areas by a subsequent step. For this purpose, a silicon wafer with an insulating intermediate layer is created, starting from a first silicon wafer comprising a surface layer on top of an insulating intermediate layer arranged on a substrate and a second silicon wafer with a surface, by bonding the respective surfaces of the two wafers and, before bonding, areas with modified layer properties are created on the first wafer within or on the surface of the surface layer which differ from the regions surrounding these areas in at least one characteristic layer property, and at least one insulating layer is subsequently applied to the surface of at least one silicon wafer, and the substrate of the first silicon wafer is removed after bonding. In a development of the method, it is advantageous to remove the substrate of the first silicon wafer selectively to the insulating intermediate layer, as selective removal can be performed by robust and comparably inexpensive process steps, such as for example by a wet chemical process. In a subsequent process step, the insulating intermediate layer of the first wafer, the previous boundary surface of the silicon/insulating layers, which was buried before the bonding, is made available as a new silicon surface by the removal, which can also take place area by area and/or step by step. Provided that the insulating intermediate layer has only been removed in certain areas, this can also be used for further process steps, for example as a mask.
An advantage of the new method in comparison to the previous state-of-the-art is that the parameters of individual areas in the uppermost silicon layer on the first wafer can be optimized for the particular type of components before bonding, without changing the parameters of the whole layer. Moreover, the surface of the first silicon layer, which has a high quality from the manufacture of the first wafer, can be made usable for further manufacturing steps with which, for example, components of integrated circuits are made without needing after-treatment of the uppermost silicon layer in order to optimize the layer quality. The new method does not depend upon the thickness of the first layer on the first silicon wafer. Particularly in the case of thicker layers, the demands upon the quality of the surface, such as for example the evenness of the layer thickness, are reduced as an insulating layer is deposited on this surface, and the surface is buried as a silicon/insulating layer boundary layer by the renewed bonding with another wafer. The demands upon the structure and quality of this layer are low as the substrate and the insulating layer of the first wafer are removed. Moreover, with the selective removal of the substrate, the intermediate layer merely serves as a stop layer, and the thickness of the insulating layer may be correspondingly thin, for example less than 0.1 &mgr;m. The thermal load and stress from the oxidation are reduced to the greatest possible extent by the low demands upon the manufacturing process of the first wafer.
In a development of the method, the conductivity is changed in defined areas of the uppermost silicon layer of the first wafer by, for example, implanting and/or diffusing a doping substance before bonding the two wafers. This enables the electrical properties of the collector regions to be adapted, particularly for bipolar transistors. Moreover, the layer thickness of the silicon layer can be locally or globally increased by means of an epitaxy process in order to create a vertical doping gradient. The electrical properties can be optimized by the combination of the various process steps, particularly i
Dietrich Harry
Dudek Volker
Schueppen Andreas
ATMEL Germany GmbH
Duy Mai Anh
Fahmy Wael
Fasse W. F.
Fasse W. G.
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