Method for manufacturing bit line

Details Method for manufacturing bit line Method for manufacturing bit line

2002-02-07

2004-06-22

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

Reexamination Certificate

active

06753265

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly to a bit line-manufacturing method, by which a bit line having a fine width can be manufactured in an easy manner.
2. Description of the Prior Art
As generally known in the art, due to the trend to make semiconductor devices highly integrated, the size of the circuit linewidth in the semiconductor device has gradually decreased. In particular, in order to ensure a process margin in a self-align contact process and in a following process of depositing an interlayer-insulating layer for electrical insulation from a conducting layer (e.g., storage node electrode of capacitor) after the bit line is formed, a bit line circuit width of less than 0.1 &mgr;m is required in products at a level of at least 1 GIGA DRAM.
However, it is actually difficult to form a bit line having such a fine width by means of the existing photo equipment. Also, in order to form a bit line having a width of less than 0.1 &mgr;m, is a photo masking process is currently carried out using an electron beam. However, this process has a problem of low productivity.
FIGS. 1A
to
1
C are cross-sectional views showing a method for fabricating a bit line according to the prior art.
According to the conventional bit line-manufacturing method as shown in
FIG. 1A
, a conducting layer
102
for forming the bit line and an insulating layer
104
are successively formed on a semiconductor substrate
100
. In this case, the insulating layer
104
serves as a hard mask while the subsequent process for forming the bit line progresses. Further, although not shown, the semiconductor substrate
100
has a structure where a transistor having a source/drain electrode region and a gate is formed.
Thereafter, a photoresist film is applied on the insulating layer
104
, exposed to light, and then developed, so that a photoresist pattern
108
covering a region, in which the bit line is formed, is formed. When conventional photo equipment is used, the photoresist pattern
108
is so patterned as to have a width of at least about 0.14 &mgr;m.
Next, as shown in
FIG. 1B
, the insulating layer is removed using the photoresist pattern as an etching mask, to thereby form a hard mask
105
. In this case, the removal of the insulating layer is carried out according to a first anisotropic dry etching process
112
.
Thereafter, the photoresist pattern is removed, and then the remnant is covered by the hard mask
105
, as shown in FIG.
1
C. Thereafter, the conducting layer is etched according to a second anisotropic dry etching process
114
, to thereby form a bit line
103
.
At this time, the bit line
103
is formed of a conducting layer remaining after the second anisotropic dry etching process, and is so patterned as to have a width of about 0.14 &mgr;m equal to that of the mask pattern.
In highly-integrated devices having a linewidth of less than 0.14 &mgr;m, however, the height of a conducting layer for forming the bit line is relatively increased due to a resistance problem of the conducting layer, whereas line and space are reduced.
Also, in the case of the bit line, in order to form a self-align contact and a contact for a storage node electrode of a capacitor in the subsequent process, an additional insulating layer for forming the hard mask is formed on the conducting layer for forming the bit line. For this reason, the height of the bit line has to be further increased.
Due to such a relative reduction of space and such a relative increase of the height of the conducting layer as described above, it is difficult to deposit the insulating film for forming the hard mask in order to insulate the bit line from the storage node electrode.
In the case where the bit line is so manufactured as to have a width of less than 0.1 &mgr;m narrower than 0.14 &mgr;m according to the conventional method, various problems occur in the course of the progress of the subsequent processes including a depositing process of the interlayer insulating film for electrical insulation between the bit line and the conducting layer and a self-align contact process. In other words, as shown in
FIGS. 2A
to
2
C and
FIG. 3
, the hard mask for forming the bit line may be damaged or broken down due to poor gap-fill of the interlayer insulating film. Also, bridges may be caused between the storage node electrodes to be formed in the subsequent processes. In addition, a contact margin may not be ensured, so that the self-align contact cannot be opened.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a bit line-manufacturing method, by which a bit line having a fine width of less than 0.1 &mgr;m can be easily manufactured.
To accomplish this object, there is provided a method of manufacturing a bit line, which comprises: successively forming a conducting layer and a hard mask on a substrate, the conducting layer serving to form a bit line,; forming a first mask pattern on the hard mask in such a manner that a sea desired region of the hard mask is exposed; isotropic dry etching the first mask pattern, so as to form a second mask pattern; etching the hard mask using the second mask pattern; removing the second mask pattern; and etching the conducting layer using the remaining hard mask, so as to form the bit line.


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patent: 08-321484 (1996-12-01), None
patent: 09-082797 (1997-03-01), None
Wolf and Tauber, “Silicon processing for the VLSI Era, vol. 1”, Chapter 16, p 539, Lattice Press, CA (1986).

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