Method for manufacturing an offset lattice bipolar transistor

Details Method for manufacturing an offset lattice bipolar transistor Method for manufacturing an offset lattice bipolar transistor

1994-09-20

1995-10-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 32, 437 55, H01L 218222

Patent

active

054551862

ABSTRACT:
An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjacent stripes are shifted or offset relative to each other. This causes the emitter pieces which are added to connect adjacent emitter stripes to be staggered with respect to each other. As a result, all sections of the emitters face a base contact and the resistance encountered along a current path between a base contact and an emitter is reduced. This results in a vertical bipolar transistor having a larger proportion of highly activated emitter, better high-frequency performance, and a reduction in thermal noise owing to transistor base resistance.

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J. G. Kassakian, M. F. Schlect & G. C. Verghese, "Section 18.8 Emitter-Current Focusing during Turn-Off," Principles of Power Electronics, pp. 521-522, Reading, Mass.: Addison-Wesley (1991).
F. Goodenough, "Tiny IC Plus FET Builds `Super LDO` Regualtor," Electronic Design, Mar. 7, 1994, pp. 45-49.
C. Simpson, "Understanding Three-Terminal Regulators," Electronic Design, Jan. 21, 1993, pp. 77-80.

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