Method for manufacturing an LCD panel

Details Method for manufacturing an LCD panel Method for manufacturing an LCD panel

2001-08-15

2003-05-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Including integrally formed optical element

C349S043000

Reexamination Certificate

active

06558971

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a display panel, particularly to a method for manufacturing an LCD panel which eliminates misalignment between the conducting line and through hole of the panel.
2. Description of the Prior Art
There are many conducting lines for connection of circuit elements on an LCD panel. A layer deposited on the conducting lines has a rough surface due to intervals between the conducting lines. This disadvantageously affects the deposition of following layers and is detrimental to the luminance of the panel. A planarization layer must be deposited on the conducting lines to eliminate these problems.
FIGS.
1
A~
1
E are diagrams showing a conventional method for manufacturing an LCD panel, wherein a planarization layer is formed on the conducting lines.
First, as shown in
FIG. 1A
, a silicon substrate
10
is provided. The substrate
10
has a copper or aluminum conducting layer forming a pad
12
a
and a conducting line
12
b
defined by a pattern of the conducting layer. The pad
12
a
is a connection terminal for a driving IC of the panel. The substrate
10
further has an oxide layer
11
on both the pad
12
a
and the conducting line
12
b
, and a nitride layer
13
only on the oxide layer
11
above the pad
12
a.
Second, as shown in
FIG. 1B
, a photoresist layer
14
is deposited, exposed and developed to form through holes
141
a
and
141
b
above the pad
12
a
and conducting line
12
b
. The through holes
141
a
and
141
b
expose the nitride layer
13
and the oxide layer
11
respectively.
Third, as shown in
FIG. 1C
, with the masking of the photoresist layer
14
, the nitride layer
13
and the oxide layer
11
exposed by the through holes
141
a
and
141
b
are etched and removed. Thus, through holes
15
a
and
15
b
exposing the pad
12
a
and conducting line
12
b
are formed. Then, the photoresist layer
14
is removed.
Fourth, as shown in
FIG. 1D
, a planarization layer
16
of photo type organic planarization material, such as PC-452 or PC403 manufactured by JSR Co. Ltd., or TRAP P202MP manufactured by TOK Co. Ltd., is deposited.
Finally, as shown in
FIG. 1E
, the planarization layer
16
is exposed and developed so that the planarization layer
16
above the pad
12
a
is removed and a through hole
17
is formed on the conducting line
12
b.
Alternatively, the planarization layer
16
can be composed of non-photo type organic planarization material. The through hole
17
is formed by depositing a photoresist layer on the planarization layer
16
, exposing and developing the photoresist layer, and etching the planarization layer with the masking of the photoresist layer.
However, in the conventional method, formation of the through hole
17
includes two exposure steps, which easily leads to a misalignment between through hole
17
and the conducting line
12
b
, as shown in FIG.
1
E.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method for manufacturing an LCD panel, which eliminates misalignment between the conducting line and through hole of the panel.
The present invention provides a method for manufacturing an LCD panel comprising the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.
In the present invention, the planarization layer is deposited before beginning the formation of the through hole. Thus, the formation of the through hole includes only one exposure step and misalignment is eliminated.


REFERENCES:
patent: 6057896 (2000-05-01), Rho et al.
patent: 6362028 (2002-03-01), Chen et al.

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