Method for manufacturing an integrated circuit chip bump electro

Details Method for manufacturing an integrated circuit chip bump electro Method for manufacturing an integrated circuit chip bump electro

1991-04-11

1993-09-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437203, H01L 21283

Patent

active

052448339

ABSTRACT:
A method for making an integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

REFERENCES:
patent: 3311966 (1967-04-01), Shaheen et al.
patent: 3495133 (1970-02-01), Miller et al.
patent: 3604989 (1971-09-01), Haneta et al.
patent: 3686698 (1972-08-01), Akeyama et al.
patent: 4029562 (1977-06-01), Feng et al.
patent: 4319264 (1982-03-01), Gangulee et al.
patent: 4386116 (1983-05-01), Nair et al.
patent: 4480288 (1984-10-01), Gazdik et al.
patent: 4552615 (1985-11-01), Amendola et al.
patent: 4675717 (1987-06-01), Herrero et al.
patent: 4739389 (1988-04-01), Goedbloed
patent: 4866507 (1989-09-01), Jacobs et al.
J. C. Edwards, "Photo-Defined Lamination For Chip Bonding" IBM Technical Disclosure Bulletin, vol. 25, No. 4., Sep. 1982, pp. 1952-1953.
R. J. Callimari, et al., "X-Ray Lithography Enhancements/Extension" IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, pp. 3451-3452.
L. Kuhn et al., "High Density, Low-Temperature Solder Reflow Bonding of Silicon Chips to Plastic Substrates" vol. 18, No. 10, Mar. 1976, p. 3477.

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