Method for manufacturing an insulated gate semiconductor device

Details Method for manufacturing an insulated gate semiconductor device Method for manufacturing an insulated gate semiconductor device

1994-10-24

1996-08-13

Dang, Trung

Fishing, trapping, and vermin destroying

437 44, 437 41, 437 45, 437 27, H01L 21265

Patent

active

055455751

ABSTRACT:
Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (15) and a P-channel transistor (16). The N-channel transistor (15) has a gate electrode (35) that has a central portion (28) and two adjacent gate extensions (49, 52). Likewise the P-channel transistor (16) has a gate electrode (35') which has a central portion (29) and two adjacent gate extensions (53, 54). The gate extensions (49, 52, 53, 54) allow the formation of graded channel regions underneath the gate electrodes (35, 35') and adjacent to the source (57, 59) and drain (58, 62) regions by offsetting an LDD or a single heavily doped source/drain implant from channel regions which are covered by the gate extensions (49, 52 53, 54).

REFERENCES:
patent: H000986 (1991-11-01), Codella et al.
patent: 4949136 (1990-08-01), Jain
patent: 4968639 (1990-11-01), Bergonzoni
patent: 5036019 (1991-07-01), Yamane et al.
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5158903 (1992-10-01), Hori et al.
patent: 5162884 (1992-11-01), Liou et al.
patent: 5171705 (1992-12-01), Choy
patent: 5182619 (1993-01-01), Pfiester
patent: 5202276 (1993-04-01), Malhi
patent: 5227321 (1993-07-01), Lee et al.
patent: 5248627 (1993-09-01), Williams
patent: 5266508 (1993-11-01), Azuma et al.
patent: 5372960 (1994-12-01), Davies et al.
patent: 5427964 (1995-06-01), Kaneshiro et al.
patent: 5445980 (1995-08-01), Komori et al.
Codella, C. F. et al., "Submicron IGFET Device With Double Implanted Lightly Doped Drain/Source Structure", IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6584-6586.

Affiliated with

Also associated with

Rating

Method for manufacturing an insulated gate semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing an insulated gate semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing an insulated gate semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1047665