Method for manufacturing an I.sup.2 L semiconductor device

Details Method for manufacturing an I.sup.2 L semiconductor device Method for manufacturing an I.sup.2 L semiconductor device

1981-02-18

1983-03-29

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148187, 148188, 148190, H01L 2126, H01L 21225

Patent

active

043779034

ABSTRACT:
An oxide layer is partially formed on an n-type region surrounded by a field oxide region. A base region of a switching transistor is formed in the n-type region using as a mask the oxide layer. Arsenic-doped polysilicon layers are selectively formed simultaneously on the surfaces of the oxide layer and the base region. Using the polysilicon layers as a mask, the emitter and collector regions of an injector transistor and the external base region of a switching transistor are formed in the n-type region and the base region respectively. Arsenic doped into the polysilicon layers is diffused into the base region, so that the collector regions of the switching transistor are self-aligned with the polysilicon layers.

REFERENCES:
patent: 4183037 (1980-01-01), LeCan et al.
patent: 4273805 (1981-06-01), Dawson et al.
Tang et al., IEDM Technical Digest, Dec. 3-5, 1979, pp. 201-204.
IBM Tech. Discl. Bulletin, vol. 22, No. 7, Dec. 1979, pp. 2786-2788.
Feth et al., "Polysilicon Merger Transistor Logic Device", vol. 22, IBM Tech. Disclosure Bull., 3388-3389 (Jan. 1980).
Middelhoek et al., "Polycrystalline Silicon as a Diffusion Source and Interconnect Layer in I.sub.2 L Realization", vol. 12, IEEE J. Solid-State Circuits, 135-138, (Apr. 1979).
Feth et al., "Layout Image for Merged Transistor Logic", vol. 22, IBM Tech. Disclosure Bull., 2948-2950 (Dec. 1979).
Isaac et al., "Method of Fabricating a Self-Aligning Vertical PNP Transistor", vol. 22, IBM Tech. Disclosure Bull., 3393-3396 (Jan. 1980).

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