Method for manufacturing an FET with asymmetrical gate region

Details Method for manufacturing an FET with asymmetrical gate region Method for manufacturing an FET with asymmetrical gate region

1990-08-29

1991-08-27

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 45, 437175, 437196, 437200, 437919, 156643, 148DIG140, H01L 2128, H01L 21338

Patent

active

050432940

ABSTRACT:
A method for manufacturing a field effect transistor having source and drain regions asymmetrically arranged relative to the gate region. A strip-shaped auxiliary layer is applied in the region of the gate. A first and second spacer are laterally fashioned along an auxillary layer, the first spacer is covered with a resist mask and the second spacer is subsequently etched away. The source metallization and the drain metallization are then applied, and a planarizing passivation layer is applied therebetween. This is followed by the application of connecting metallizations for the source, drain and gate regions.

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