Method for manufacturing a wafer level package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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Details

C438S117000, C438S612000, C257S692000, C257S737000, C257SE23021, C257SE23015

Reexamination Certificate

active

07867817

ABSTRACT:
A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible.

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patent: 10 2006 0024451 (2006-03-01), None

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