Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2011-01-11
2011-01-11
Maldonado, Julio J (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S117000, C438S612000, C257S692000, C257S737000, C257SE23021, C257SE23015
Reexamination Certificate
active
07867817
ABSTRACT:
A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible.
REFERENCES:
patent: 6245595 (2001-06-01), Nguyen et al.
patent: 6462414 (2002-10-01), Anderson
patent: 6521970 (2003-02-01), Takiar et al.
patent: 7132312 (2006-11-01), Huang et al.
patent: 2002/0130412 (2002-09-01), Nagai et al.
patent: 2005/0070049 (2005-03-01), Cheng et al.
patent: 2005/0202593 (2005-09-01), Chen et al.
patent: 2006/0003569 (2006-01-01), Farnworth et al.
patent: 2006/0186540 (2006-08-01), Buchwalter et al.
patent: 2007/0020916 (2007-01-01), Farnworth
patent: 10 2001 0045280 (2001-06-01), None
patent: 10 2001 0105641 (2001-11-01), None
patent: 10 2006 0024451 (2006-03-01), None
Dobritz Stephan
Hedler Harry
Mieth Henning
Economou John S.
Maldonado Julio J
Qimonda AG
Scarlett Shaka
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