Method for manufacturing a trench capacitor of a one-transistor

Fishing – trapping – and vermin destroying

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437 47, 437 48, 437 60, 437919, H01L 2170

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050735152

ABSTRACT:
Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned cooperating capacitor electrode. In a one-transistor memory cell having a trench capacitor in a semiconductor substrate (1), a field oxide (3) that isolates different cells is exploited for a self-aligning process. After the formation of a first electrode and of a dielectrode (5) of the capacitor, a conductive layer (6) is applied surface-wide, the upper edge thereof being higher over the field oxide (3) than over the field-oxide-free locations of the substrate (1). The raised location is exposed in a re-etching process upon employment of a planarizing auxiliary layer (9), and a sub-layer (10, 10') is selectively applied thereon, either by local oxidation, selective or non-selective deposition. This sub-layer (10, 10') serves as a self-aligned mask for the structuring of the conductive layer (6) as a cooperating electrode of the trench capacitor.

REFERENCES:
patent: 4045783 (1977-08-01), Harland
patent: 4752819 (1988-06-01), Koyama
"Isolation Merged Stacked Dynamic Random Access Memory Cell", IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988, pp. 39-42.
"Methods of Preventing Excessive Oxidation of Polysilicon Trench Fill in Semiconductor Devices", IBM Technical Disclosure Bulletin, vol. 30, No. 10, Mar. 1988, pp. 156-158.
"An Experimental 16Mbit CMOS DRAM Chip with a 100 MHZ Serial Read/Write Mode", by Shigeyoshi Watanabe et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1982, pp. 763-768.
"A Double Epitaxial Process for High Density DRAM Trench Capacitor Isolation", by Chen et al., IEEE Electron Device Letters, vol. Edl. 8, No. 11, Nov. 1987.
"Technologie Hochintegrierter Schaltungen", by D. Widmann et al., Springer-Verlag, pp. 270-271.

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