Fishing – trapping – and vermin destroying
Patent
1992-12-18
1995-06-06
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 51, 437 60, 437235, 437248, 437983, 437195, 148DIG117, H01L 2184, H01L 2198
Patent
active
054222931
ABSTRACT:
A TFT panel is manufactured by a process of forming an oxide voltage-apply lines, gate lines, and capacitor lines on an insulating substrate, and a process of forming thin-film transistors, pixel electrodes, data lines, and ground lines. In a state that one end of the gate line and both ends of the capacitor line are connected to the oxide voltage-apply line, oxide films are formed on the surfaces of the gate line and the capacitor line by anodization. After forming the oxide film, the gate line and the capacitor line are electrically separated from the oxide voltage-apply line.
REFERENCES:
patent: 4871234 (1989-10-01), Suzuki
patent: 5028122 (1991-07-01), Hamada et al.
patent: 5086009 (1992-02-01), Sangouard
patent: 5128786 (1992-07-01), Yanagisawa
patent: 5146301 (1992-09-01), Yamamura et al.
patent: 5162901 (1992-11-01), Shimada et al.
Casio Computer Co. Ltd.
Hearn Brian E.
Trinh Michael
LandOfFree
Method for manufacturing a TFT panel does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a TFT panel, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a TFT panel will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-987320