Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2007-02-15
2010-12-28
Gurley, Lynne A. (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S107000, C438S125000, C438S118000, C438S613000, C257S734000, C257SE21503
Reexamination Certificate
active
07858437
ABSTRACT:
An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.
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Office Action issued in corresponding Chinese Patent Application No. 2007100793501 on Jun. 20, 2008.
Japanese Office Action dated Jan. 19, 2010 and issued in corresponding Japanese Patent Application 2007-007727.
Jung Hoe-Ku
Kang Myung-Sam
Kim Ji-Eun
Park Jung-Hyun
Gurley Lynne A.
Im Junghwa M
Samsung Electro-Mechanics Co. Ltd.
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