Method for manufacturing a stacked electrode for a semiconductor

Details Method for manufacturing a stacked electrode for a semiconductor Method for manufacturing a stacked electrode for a semiconductor

1997-05-28

1999-07-27

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438963, 438703, 438257, 438261, 438593, H01L 21312, H01L 213105, H01L 21283

Patent

active

059289660

ABSTRACT:
A method for making a stacked gate electrode structure for a semiconductor device provides for three layers of the stacked structure including a first conductive layer, an insulating layer, and a second conductive layer. The layers of the stacked structure are to be of uniform width. The method includes forming on a gate oxide layer on the surface of the semiconductor substrate a first conductive layer, an insulating layer, and a second conductive layer in order. A photoresist is formed on the second conductive layer and patterning of the second conductive layer and the insulating layer using the photoresist as an etching mask is carried out. Side wall covering layers which result from the insulating layer patterning which cover the sides of both the second conductive layer and the insulating layer are removed. Thereafter, the first conductive layer is patterned using the photoresist as an etching mask.

REFERENCES:
patent: 4616402 (1986-10-01), Mori
patent: 5660681 (1997-08-01), Fukuda et al.
Allred, D., et al., "Film redeposition on vertical surfaces during reactive ion etching", J. Vac. Sci., 7(3), pp. 505-511. 1989.
Wolf, S. and Tauber, R.N., "Silicon Processing for the VLSI Era--vol. 1, Process Technology" (Sunset Beach CA: Lattice Press): 564-565 1986.

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