Method for manufacturing a SOI wafer

Details Method for manufacturing a SOI wafer Method for manufacturing a SOI wafer

2000-12-29

2003-01-14

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

C438S309000, C438S341000

Reexamination Certificate

active

06506658

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating a silicon-on-insulator (SOI) wafer suitable to manufacture semiconductor electronic devices. The wafer includes a substrate of monocrystalline silicon having a doped region buried therein.
BACKGROUND OF THE INVENTION
As an alternative to wafers made of only silicon, there are composite wafers. In recent years in the microelectronic industry, composite wafers have been proposed. Composite wafers are known as SOI wafers, which comprise at least two silicon layers. One of the which is thinner than the other, and an isolation layer of silicon oxide is between the two silicon layers. For a discussion on SOI wafers, reference can be made, for instance, to the article “Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations” by Hausman et al., Japanese Journal of Applied Physics, Vol. 28, No. 8, August 1989, pages 1426-1443.
The Silicon-On-Insulator isolation technology has recently aroused considerable interest because integrated circuits having a substrate formed of SOI wafers have several advantages over circuits formed on traditional substrates made of monocrystalline silicon only. The main advantages are as follows: a reduction in the parasitic capacitance; increase in the switching speed; a greater immunity to noise; less leakage currents; no latch-up of parasitic components; greater resistance to radiation effects; and an increase of the component packaging density.
However, the application of integrated devices based on SOI substrates is severely limited, in particular, by the high cost of SOI wafers. As described in the above referenced article, a typical method of manufacturing SOI wafers comprises bonding two wafers of monocrystalline silicon together. According to such a process, one of the two wafers is subjected to an oxidation step, which allows formation of an oxide layer on one surface. The oxide layer surface is then cleaned and bonded to the other wafer. The SOI wafers thus obtained exhibit excellent electrical characteristics but are cost-intensive.
Another method, commonly known as SIMOX (Separation by IMplants of OXygen), comprises the implantation of oxygen atoms into the wafer to bring the oxide thickness into the 100 to 200 nm range. This and other methods are described in an article “SOI Technologies: Their Past, Present and Future” by J. Haisha, Journal de Physique, Colloque C4, Supplement an N. 9, Tome 49, September 1988. Although these techniques produce the SOI structure using a single wafer, they have certain disadvantages. These disadvantages include the inability to accept the application of high voltages, as in case of SIMOX technology, and the high fault rate due to crystal defects produced by the stress induced by the buried oxide.
Another known method of fabricating SOI wafers at a low cost is described in the European Patent No. 98830299.8 and dated May 15, 1998. This application is incorporated herein by reference in its entirety, and is assigned to the assignee of the present invention. This method comprises the following steps. A substrate of monocrystalline silicon is subjected to a thermal oxidation step to grow a silicon oxide layer over its surface. Certain oxide areas are removed, wherein ions with dopant opposite to the substrate are implanted and diffused. This is done to provide a number of areas with dopants opposite the substrate, which are beneath the top surface of the substrate. An epitaxial layer is grown with the same dopant and concentration as the substrate.
The method further includes again subjecting the semiconductor to a thermal oxidation step, and etching to define trench-like openings extending from the surface to the buried regions. The wafer is dipped into an electrolytic solution in a galvanic cell. The wafer is subjected to a selective electrochemical etching step of the areas having an opposite dopant to the substrate, resulting in porosity formation. The wafer is further subjected to thermal oxidation so that the porous regions are changed into oxidized regions. The oxidized regions are removed to leave a buried cavity, and new oxidation fills in the trench-like openings and the buried cavity with oxide.
Although in many ways advantageous, this method has a drawback in that the processing sequence described above is burdened with a large number of steps. Furthermore, a fairly high rate of crystal defects is to be expected from such a sequence. Since the rate of thermal oxidation is not constant along all the walls of the structure, and especially at the corners thereof, some of the trench-like openings will tend to close in advance. This causes a wedging effect and a consequent high stress, which will be relieved through the formation of crystal defects.
SUMMARY OF THE INVENTION
The underlying technical problem of the present invention is to provide a low-cost method of fabricating SOI wafers showing a high yield, and which is suitable to manufacture electronic devices monolithically integrated on a semiconductor.
The concept behind this invention is one of turning the doped buried region, which is trapped within the substrate of monocrystalline silicon, into a region of porous oxide having electrical and physical properties similar to those of a thermal oxide.
Briefly stated, according to the invention the method comprises a step of forming trench-like openings extended from the substrate surface to the buried region. A selective etching step is performed, which is to be carried out through the openings in order to turn the buried region of monocrystalline silicon into porous silicon. The porous silicon is oxidized to produce an insulating portion of the SOI wafer.


REFERENCES:
patent: 5686342 (1997-11-01), Lee
patent: 6140196 (2000-10-01), Tung
patent: 0226091 (1987-06-01), None
patent: 2564241 (1985-11-01), None
patent: 93/10559 (1993-05-01), None

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