Method for manufacturing a semiconductor memory device

Details Method for manufacturing a semiconductor memory device Method for manufacturing a semiconductor memory device

2001-07-31

2003-07-22

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S726000, C438S704000

Reexamination Certificate

active

06596645

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device and, more particularly, to a method for manufacturing a semiconductor memory device which is capable of preventing deterioration of the semiconductor memory device resulting from plasma etching.
DESCRIPTION OF THE PRIOR ART
A memory device provides a means for storing and retrieving data. Certain types of semiconductor memory devices, e.g., dynamic random access memory (DRAM) devices are characterized by small size, high reliability, commodity pricing and high speed operation.
In semiconductor memory devices utilizing a ferroelectric material as a capacitor dielectric, several approaches have been developed for overcoming the need to refresh the data as in a conventional DRAM and to achieve a large capacitance. A ferroelectric random access memory (FeRAM) is a type of nonvolatile memory device that can maintain stored information in a power-off state and can provide operating speeds comparable to those of conventional DRAMs.
Strontium bismuth tantalate, SrBi
2
Ta
2
O
9
(SBT), or lead zirconate titanate, Pb(Zr
x
, Ti
1−x
)O
3
(PZT), are materials commonly used as the ferroelectric material in FeRAM devices. A ferroelectric material that has a dielectric constant on the order of 10
2
-10
3
at room temperatures and has two stable residual polarization states. These properties, therefore, render such ferroelectric materials suitable for use in nonvolatile memory devices. Nonvolatile memory devices utilizing ferroelectric materials input data by setting the orientation of the polarization by applying an electric field. Once the orientation of the residual or remnant polarization is set, the electric field may be removed without losing the digital data, i.e., the stored “1” or “0”, stored in the FeRAM.
The process for manufacturing FeRAM devices utilizes fairly conventional DRAM methods including a first interlayer dielectric (ILD) oxide layer formed on a semiconductor substrate over a bottom structure, e.g., a transistor and a bottom electrode. A ferroelectric layer and a top electrode are sequentially laminated on the first ILD layer to form a capacitor and a second ILD oxide layer is formed over the whole structure to cover the capacitor. Finally, contact holes are formed to expose a portion of the top electrode and a portion of the bottom electrode for electrical connection.
Conventional plasma etch processes can utilize a variety of plasma generating devices, e.g., reactive ion etching (RIE), induced coupled plasma (ICP), electron cyclotron resonance (ECR) and transformer coupled plasma (TCP), to generate plasma having a high ion density D
i
, a high electron density D
e
and capable of etching an oxide layer. The ferroelectric materials used in FeRAM devices are, however, fragile and easily damaged during the plasma etch process. Accordingly, the residual polarization P
r
and the coercive voltage V
c
are reduced and less uniform, changes that will, in turn, degrade the resulting FeRAM device reliability. To solve this problem, a recovery annealing process should be carried out after performing plasma dry etching.
FIG. 1A
is a graph illustrating results achieved using the conventional plasma etching condition for etching an ILD oxide layer covering the capacitor in a FeRAM device. The electron temperature T
e
is relatively fixed, though the electron density D
e
and the ion density D
i
are increased in each of the plasma conditions
1
,
2
,
3
or
4
which are achieved by setting different process conditions, mainly modification of the injection gas flows.
FIGS. 1B and 1C
are graphs showing the residual polarization P
r
and the coercive voltage V
c
change when an etching is carried out in the same condition of FIG.
1
A. The cumulative probability, as reflected in
FIGS. 1B and 1C
, is the probability of getting specific ranges between a maximum value and a minimum value for dP and dV on the x-axis in accordance with the conditions
1
,
2
,
3
and
4
respectively. This is the cumulative probability means the probability of a specific value which is obtained between the minimum values and the maximum values under the conditions
1
,
2
,
3
and
4
. As shown in
FIGS. 1B and 1C
, as D
e
and D
i
are increased, the P
r
and the V
c
are decreased. That is, a deterioration of the FeRAM capacitor characteristics is unavoidable by increasing of D
e
and D
i
.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a ferroelectric memory device that prevents deterioration of the ferroelectric capacitor characteristics induced by increased electron density D
e
and ion density D
i
during the ILD etching process to form an opening in the ILD layer and expose a portion of the ferroelectric capacitor.
In accordance with an aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method comprising the steps of forming an interlayer dielectric (ILD) layer on an upper part of a semiconductor substrate provided with a capacitor structure and etching the ILD layer to expose a portion of the capacitor structure under conditions in which the electron temperature of the plasma is maintained in a range between 2.0 eV and 4.0 eV.


REFERENCES:
patent: 5838111 (1998-11-01), Hayashi et al.
patent: 6093457 (2000-07-01), Okumura et al.
patent: 6129806 (2000-10-01), Kaji et al.
patent: 6231777 (2001-05-01), Kofuji et al.
patent: 6261406 (2001-07-01), Jurgensen et al.
patent: 6306247 (2001-10-01), Lin

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