Method for manufacturing a semiconductor integrated circuit util

Metal working – Method of mechanical manufacture – Assembling or joining

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29578, 29580, 29591, 148 15, 148174, 148187, 148188, 156628, 156657, 156662, 357 59, 357 92, H01L 21225, H01L 2131

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044047371

ABSTRACT:
A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the polycrystalline silicon layers constituting first electrode wirings to the second conductivity regions; forming a thick oxidation film on the polycrystalline silicon layers and a thin oxidation film on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film to form a second electrode wiring to the first conductivity region, said second electrode wiring being insulated from the polycrystalline silicon layers by the thick oxidation film. The method provides integrated circuits such as I.sup.2 L circuits which are capable of high speed operation and a high packaging density.

REFERENCES:
patent: 3667008 (1972-05-01), Katnack
patent: 3940288 (1976-02-01), Takagi et al.
patent: 4084174 (1978-04-01), Crippen et al.
patent: 4106049 (1978-08-01), Shinozaki et al.
patent: 4139402 (1979-02-01), Steinmaier et al.
patent: 4148055 (1979-04-01), Edlinger et al.
patent: 4157269 (1979-06-01), Ning et al.
patent: 4160989 (1979-07-01), Brebisson et al.
patent: 4190466 (1980-02-01), Bhattacharyya et al.
patent: 4210993 (1980-07-01), Sunami
Berger et al., "Investigation--MTL/I.sup.2 L", IEEE J. Solid State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 327-336.
Isaac et al., "Method for Fabricating Self-Aligned . . . Transistor", I.B.M. Tech. Discl. Bull., vol. 22, No. 8a, Jan. 1980, pp. 3393-3396.

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