Method for manufacturing a semiconductor integrated circuit incl

Details Method for manufacturing a semiconductor integrated circuit incl Method for manufacturing a semiconductor integrated circuit incl

1990-05-16

1991-06-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 51, 437150, 437153, 437978, 148DIG106, H01L 21331

Patent

active

050231952

ABSTRACT:
After a base region and a base contact region, a diffused resistance region and a pair of contact regions formed at each end of the diffused resistance region are formed, an silicon oxide film of essentially uniform thickness is formed anew on the surface of an epitaxial layer. In the silicon oxide film, a collector contact/doping window, a base contact window, an emitter contact/doping window, a lower layer electrode contact window, and a diffused resistance element contact window are formed simultaneously, then the base contact region and the diffused resistance element contact regions are shielded by a mask and a collector contact region, an emitter contact region, and a lower layer electrode contact region are doped. The method of manufacturing a semiconductor integrated circuit of the present invention has the advantages that all insulating films have a uniform film thickness, eliminates the problems of side etching when the contact windows or dopant windows are formed or of etching the element regions. It is possible to form element regions of the design size and a large margin of spacing for the isolating regions and the base region is unnecessary. A high degree of integration can be achieved.

REFERENCES:
patent: 4009057 (1977-02-01), de Brebisson et al.
patent: 4573257 (1986-03-01), Hulseweh
patent: 4721686 (1988-01-01), Contiero et al.
patent: 4902633 (1990-02-01), Cambou
patent: 4910160 (1990-03-01), Jennings et al.

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