Method for manufacturing a semiconductor integrated circuit devi

Details Method for manufacturing a semiconductor integrated circuit devi Method for manufacturing a semiconductor integrated circuit devi

1977-01-25

1979-12-04

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 357 45, H01L 2122

Patent

active

041770960

ABSTRACT:
In manufacturing an insulated gate field effect transistor integrated circuit using both a self-alignment diffusion process and a non-self-alignment diffusion process, a mask is formed having a combined pattern of areas at which a subsequent self-alignment diffusion and a non-self-alignment diffusion will occur. An oxidation prevention layer for preventing thermal oxidation of a substrate is selectively formed on a semiconductor substrate using the prepared mask. Those areas of the semiconductor substrate which are not covered by the oxidation prevention layer are oxidized by thermal oxidation to form oxidized layers thereon, and impurities are diffused first in the areas of the substrate corresponding to the non-self-alignment portion of the mask pattern and subsequently in the areas of the substrate corresponding to the self-alignment portions of the mask pattern to build in an insulated gate field effect transistor network. According to the present method, the height of stepped areas produced in the insulating layer on the semiconductor substrate are minimized so that the breakage of the metallized pattern which extends over the stepped areas is prevented.

REFERENCES:
patent: 3865651 (1975-02-01), Arita
patent: 3893152 (1975-07-01), Lin
patent: 3921282 (1975-11-01), Cunningham et al.
patent: 3921283 (1975-11-01), Shappir
patent: 3933540 (1976-01-01), Kondo et al.
patent: 3985591 (1976-10-01), Arita
patent: 3996077 (1976-12-01), Verkuijlen
patent: 4008107 (1977-02-01), Hayasaka et al.
patent: 4021789 (1977-05-01), Furman et al.

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