Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2005-01-04
2005-01-04
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S197000, C438S216000, C438S257000, C438S258000, C438S261000, C438S266000, C438S275000, C438S591000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S368000, C257S382000, C257S384000, C257S390000, C257S499000
Reexamination Certificate
active
06838320
ABSTRACT:
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.
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Fujii et al., “A Thermally Stable Ti-W Salicide for Deep-Submicron Logic with Embedded DRAM”, IEDM, 1996, pp. 451-454.
Ootsuka Fumio
Tokunaga Takafumi
Yoshida Makoto
Antonelli Terry Stout & Kraus LLP
Renesas Technology Corp.
Soward Ida M.
Trinh Michael
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