Method for manufacturing a semiconductor integrated circuit

Details Method for manufacturing a semiconductor integrated circuit Method for manufacturing a semiconductor integrated circuit

1990-04-18

1992-08-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 59, 437 76, 148DIG9, 148DIG10, H01L 2122

Patent

active

051418819

ABSTRACT:
A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

REFERENCES:
patent: 3730786 (1973-05-01), Ghosh
patent: 4826780 (1989-05-01), Takemoto
patent: 4914051 (1990-04-01), Huie
IBM Technical Disclosure Bulletin, vol. 20, No. 12 May 1978, pp. 5175-5177.

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