Patent
1988-05-27
1991-07-09
Wojciechowicz, Edward J.
357 35, 357 44, 357 48, H01L 2702
Patent
active
050310194
ABSTRACT:
A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.
REFERENCES:
patent: 4825275 (1989-04-01), Tomassetti
Hikawa Tetsuo
Kosaka Daisuke
Nishikawa Masami
Ueda Yoshinori
Ricoh & Company, Ltd.
Wojciechowicz Edward J.
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