Method for manufacturing a semiconductor device having interconn

Details Method for manufacturing a semiconductor device having interconn Method for manufacturing a semiconductor device having interconn

1996-05-06

1998-02-24

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437978, 437924, H01L 21283

Patent

active

057211574

ABSTRACT:
A method for manufacturing a semiconductor device comprises, after sequentially forming first and second insulating films over a semiconductor substrate, forming a lower interconnection layer formation groove by a lithography technique and anisotropic etching technique in the second insulating film and first insulating film. Then a lower interconnection layer material is formed over a whole surface of a resultant structure and it is removed, by a chemical/mechanical polishing technique, in a way to leave a portion as a buried interconnection layer in the lower interconnection layer formation groove. Then first and second insulating interlayers are subsequently formed over a whole surface of a resultant structure and an upper interconnection layer formation groove is formed in the second insulating interlayer. Then a via hole is formed in the first insulating interlayer at an area connecting an upper interconnection layer to a lower interconnection layer. The formation of the via hole is achieved by setting an etching rate of the first insulating interlayer to be over ten times that of the second insulating film and second insulating interlayer. After the formation of the via hole, an upper interconnection layer is formed as a buried layer in the upper interconnection formation groove and via hole and it is electrically connected to the lower interconnection layer.

REFERENCES:
patent: 4966870 (1990-10-01), Barber et al.
patent: 5244837 (1993-09-01), Dennison
patent: 5258328 (1993-11-01), Sunada et al.
patent: 5371047 (1994-12-01), Greco et al.
patent: 5451543 (1995-09-01), Woo et al.

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