Method for manufacturing a semiconductor device having a phospho

Details Method for manufacturing a semiconductor device having a phospho Method for manufacturing a semiconductor device having a phospho

1989-10-30

1991-04-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437978, 437240, 437228, 437982, 148DIG133, H01L 21441

Patent

active

050047043

ABSTRACT:
A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.

REFERENCES:
patent: 4349584 (1982-09-01), Flatley et al.
patent: 4743564 (1988-05-01), Sato et al.
patent: 4782037 (1988-11-01), Tomozawa et al.
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4879253 (1989-11-01), Wakamatsu
"Barrier for Preventing Titanium Silicide Oxidation During Glass Reflow" IBM Tech. Disclosure Bulletin; vol. 31; 11/88.
VLSI Technology, Edited by S. M. Sze, Bell Laboratories, Inc., McGraw-Hill Book Company, pp. 112-129, 1983.

Affiliated with

Also associated with

Rating

Method for manufacturing a semiconductor device having a phospho does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a semiconductor device having a phospho, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor device having a phospho will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-326687