Method for manufacturing a semiconductor device having a...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S425000, C438S443000

Reexamination Certificate

active

06797588

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-101597 filed on Mar. 30, 2001.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a silicon oxide film is thermally formed on an inner surface of a trench in a semiconductor layer and to a method for manufacturing the device. The present invention is preferably applied to trench-gate type semiconductor devices.
At an end corner of the sidewall of a trench gate, electric-field tends to concentrate, and a gate insulating film tends to be relatively thin, which results in poor breakdown voltage at the corner. As shown in
FIG. 9
, it has been proposed to alleviate the electric-field concentration and the thinning of the insulating film J
1
by rounding the end corner J
2
. It is also proposed to improve the resistance of the insulating film against electric-field intensity by using a thick silicon oxide film or an ONO film, which consists of a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer, as the insulating film.
However, the above proposed methods have the difficulties mentioned below. In order to round the corner, thermal oxidization, oxide film removal, and isotropic etching need to be repeated, so the sidewall of the trench is etched, and the width of the trench deviates. That causes deviation in the device characteristics. If the thickness of the silicon oxide film is increased, the thickness of the oxide film at a channel region is also increased. That also causes deviation in the device characteristics.
The inventors of the present invention proposed a trench-gate type semiconductor device manufactured by steps shown in
FIGS. 10A-10D
, in which the ONO film is used. As shown in
FIG. 10A
, after forming a trench J
3
, a thermal silicon oxide film J
4
is formed on the inner surface of the trench J
3
. A predetermined thickness of the silicon oxide film J
4
in the trench J
3
is removed. Then, a silicon nitride film J
5
is deposited on the silicon oxide film J
4
, as shown in FIG.
10
B. The silicon nitride film J
5
is anisotropically etched to leave the film J
5
only on the sidewall of the trench J
3
, as shown in FIG.
10
C. Finally, another silicon oxide film J
7
is thermally formed on the silicon nitride film J
5
and the silicon oxide films J
4
. Thus, a thicker silicon oxide film is formed at both upper end corner J
6
and lower end corner J
8
of the sidewall of the trench J
3
, as shown in FIG.
10
D.
However, the proposed process using the ONO film creates an overhang at the upper corner J
6
of the trench J
3
after the silicon oxide film J
7
is formed, as shown in FIG.
11
. The overhang causes a void J
10
after a polycrystalline silicon layer J
9
for forming a gate electrode is deposited. The void J
10
also causes deviation in the device characteristics.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems, and an object is to thicken an insulating film at an upper corner of the sidewall of a trench, while the film thickness of a gate insulating film at a channel region and the cross-sectional profile of the trench are controlled.
A surface of a semiconductor substrate is selectively etched to form the opening of a trench. A thick insulating film is deposited on the surface. An inner opening, which is narrower than the trench opening, is formed in the insulating film within the trench opening. The insulating film may be formed using a LOCOS (i.e., local oxidization of silicon) oxide film having so called bird's beak. An inner region of the trench, the width of which is the same as that of the inner opening, is formed by etching using the insulating film as an etching mask. The inner surface of the trench is thermally oxidized to form a silicon oxide film, and the silicon oxide film and the USG film form a gate insulating film. A gate electrode is formed in the trench. In this trench structure, the gate insulating film is relatively thick at its upper corners, so the breakdown voltage at the corners is increased.


REFERENCES:
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patent: 5330927 (1994-07-01), Lee
patent: 5447883 (1995-09-01), Koyama
patent: 5480832 (1996-01-01), Miura et al.
patent: 5541425 (1996-07-01), Nishihara
patent: 5648283 (1997-07-01), Tsang et al.
patent: 6259143 (2001-07-01), Tasaka
patent: 6448139 (2002-09-01), Ito et al.
patent: 6469345 (2002-10-01), Aoki et al.
patent: 6482701 (2002-11-01), Ishikawa et al.
patent: 6521538 (2003-02-01), Soga et al.
patent: 2002/0167096 (2002-11-01), Aoki et al.
patent: A-61-226966 (1986-10-01), None
patent: A-63-133665 (1988-06-01), None
patent: A-7-183400 (1995-07-01), None
patent: A-11-45935 (1999-02-01), None
U.S. patent application Ser. No. 10/175,294, Aoki et al., filed Jun. 20, 2002.
U.S. patent application Ser. No. 09/630,786, Ishikawa et al., filed Aug. 2, 2000.
U.S. patent application Ser. No. 09/758,377, Aoki et al., filed Jan. 12, 2001.
U.S. patent application Ser. No. 09/790,888, Soga et al., filed Feb. 23, 2001.
U.S. patent application Ser. No. 09/875,026, Ito et al., filed Jun. 7, 2001.

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