Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-12-17
2004-01-20
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S427000, C438S429000
Reexamination Certificate
active
06680238
ABSTRACT:
BACKGROUND
1. Technical Field
Methods for manufacturing semiconductor devices and, more particularly, methods for manufacturing semiconductor devices are disclosed which are capable of forming a shallow trench isolation and a deep trench isolation in a straight line of the same substrate by using only one etching process without an any additional etching process when the shallow trench isolation and the deep trench isolation are formed to form a trench with an appropriate depth on the semiconductor substrate and fill an insulating layer within the trench.
2. Description of the Related Art
As the degree of integration of semiconductor devices increases, the design rule is reduced. Accordingly, a conventional device isolation method such as local oxidation of silicon (LOCOS), R-LOCOS (Recessed LOCOS), PSI (Partial Si Etch Isolation), PBL (Poly-Buffered LOCOS) and the like has reached to a critical point since the size of a device isolation layer to isolate between semiconductor devices is scaled down by the same scale.
In order to solve the above-described problem, deep trench isolation (hereinafter, DTI) has been introduced as a further isolation technique.
More recently, device isolation layers have been formed by utilizing simultaneously a shallow trench isolation (STI) and DTI to isolate between semiconductor devices.
FIGS. 1
a
to
1
c
are cross-sectional views in sequence for representing a conventional method for forming a device isolation layer of a semiconductor device.
As shown in
FIG. 1
a
, after a first photoresist layer
20
is deposited on a semiconductor substrate
10
with a predetermined substructure, a first photoresist layer
20
having a predetermined shape is obtained by patterning the first photoresist layer
20
into the predetermined shape to form a plurality of STIs
30
. Then, the plurality of STIs
30
are formed in the semiconductor substrate
10
by etching the semiconductor substrate
10
to a first predetermined depth using the first photoresist layer
20
having a predetermined shape as a mask.
Thereafter, as shown in
FIG. 1
b
, after the first photoresist layer
20
having the predetermined shape is removed, a second photoresist layer
40
is formed on the semiconductor substrate
10
from which the first photoresist layer
20
having the predetermined shape is removed. Subsequently, the second photoresist layer
40
of the predetermined shape is obtained by pattering the second photoresist layer
40
into the predetermined shape to form a DTI.
Also, a predetermined region of the semiconductor substrate
10
formed with the STIs
30
is etched deeper as compared to the previous etching process by using the second patterned photoresist layer
40
as a mask, thereby forming the DTI
50
.
As shown in
FIG. 1
c
, by removing the second photoresist layer
40
the STI
30
and the DTI
50
are formed on the semiconductor substrate
10
.
However, during the second etching process, if the pattern of the second photoresist layer
40
does not match the profile of the STI
30
, there is a problem that the STI
30
and the DTI
50
cannot be formed on a straight line since the STI
30
and the DTI
50
are mismatched in an “A”, as shown in
FIG. 1
c.
Also, the inside of the STI
30
and the DTI
50
are damaged by plasma generated during the first and second etching processes.
SUMMARY OF THE DISCLOSURE
To solve the above-mentioned problems associated with conventional methods for manufacturing semiconductor devices, a method for manufacturing a semiconductor device is disclosed which is capable of simplifying a semiconductor isolation forming process as well as minimizing damage caused from plasma to form a shallow trench isolation and a deep trench isolation on a straight line of the same substrate using only one etching process without any additional etching process when the shallow trench isolation and the deep trench isolation are formed to form a trench with an appropriate depth on the semiconductor substrate and fill an insulating layer within the trench.
One disclosed method for manufacturing a semiconductor device comprises forming first and second deep trench isolations within a semiconductor substrate by performing an etching process using a first photoresist layer pattern formed at a predetermined region on the semiconductor substrate in which a pad oxide layer and a nitride layer are sequentially formed; forming a barrier layer on an inside wall of the second deep trench isolation by performing a nitriding process after removing the first photoresist layer pattern and forming a second photoresist layer pattern at a region formed with the first deep trench isolation on the resultant material; and forming a shallow trench isolation by removing the second photoresist layer pattern and then growing silicon in the first deep trench isolation region covered with the second photoresist layer pattern by performing a silicon epitaxial growth process.
In the disclosed methods, a barrier layer made of an oxide or nitride is formed by processing at low power and low pressure in a chamber in which the processes of forming and etching the deep trench isolation is performed and silicon in the deep trench isolation is grown by maintaining a furnace at a temperature ranging from about 500° C. to about 1100° C.
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patent: 6020230 (2000-02-01), Wu
patent: 6486039 (2002-11-01), Yoo et al.
patent: 6518146 (2003-02-01), Singh et al.
patent: 2002/0070420 (2002-06-01), Oh et al.
patent: 11-097519 (1999-04-01), None
Hynix / Semiconductor Inc.
Quach T. N.
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