Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2002-07-11
2004-05-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
Reexamination Certificate
active
06740564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and specifically to a semiconductor device comprising a plug for connecting between an upper conductive layer and a lower conductive layer.
2. Background Art
In recent semiconductor devices, a plug made of tungsten (W) is frequently used as a plug structure for filling a contact hole or a via hole. Known methods for forming tungsten plugs include a method utilizing etch back, and a method utilizing CMP (chemical mechanical polishing).
In the etch-back method, metal wiring must be embedded in the plug recess portion after forming a plug. On the other hand, in the plug forming method using CMP, since embedding of such metal wiring is not required, and the foreign matter formed in the formation of the tungsten film and the etch back of tungsten can be removed by CMP, short-circuiting between wirings can be reduced. Therefore, the plug forming method using CMP is becoming the main stream of plug forming.
In the plug forming method using CMP, aiming at the removal of metal contamination and foreign matter after polishing, cleaning with hydrogen fluoride (HF), which is inexpensive and easy to handle, is frequently used.
However, in the tungsten plug forming method using CMP, the degradation of electrical properties of wiring caused by voids, seams, or the like formed in the tungsten plug forming was unavoidable. Problems arisen in a conventional tungsten plug forming method will be described below referring to the drawings.
FIGS. 7A and 7B
are schematic sectional views showing a method for forming a tungsten plug using CMP.
FIG. 7A
shows the state where after forming an interlayer insulating film
102
on an underlying wiring layer
101
to form a contact hole, and sequentially forming a titanium film
103
and a titanium nitride film
104
so as to cover the internal wall of the contact hole, a tungsten film
105
is formed using the CVD method to fill the contact hole. Here, the underlying wiring layer
101
may be a semiconductor substrate. In the state where the contact hole has been filled with the tungsten film
105
, a seam portion
106
has been formed in the contact hole.
FIG. 7B
shows the state where the tungsten film
105
on the interlayer insulating film
102
has been removed by polishing using CMP after the state shown in
FIG. 7A
, and the product has been cleaned using a hydrogen fluoride (HF) solution. By the removal of the tungsten film
105
on the interlayer insulating film
102
, the tungsten film
105
fills only the inside of the contact hole
107
, and a tungsten plug consisting of the tungsten film
105
is formed.
As
FIG. 7B
shows, since the hydrogen fluoride solution dissolves the titanium film
103
between the tungsten film
105
and the interlayer insulating film
102
rapidly in cleaning, the interlayer insulating film
102
positioned outside the contact hole moves back, and a gap
108
is formed.
If the gap
108
reaches the underlying wiring layer (or semiconductor substrate)
101
, the underlying wiring layer (or semiconductor substrate)
101
is removed by hydrogen fluoride, and a void
109
as shown in
FIG. 7B
is formed.
A problem of increase in via resistance and contact resistance has arisen by the formation of such a void
109
. Also, the void
109
has caused open defects to occur. Thereby, increase in the speed of semiconductor devices has been disturbed, and the reliability of semiconductor devices has been lowered.
In the state after polishing shown in
FIG. 7B
, since the tungsten film
105
on the seam portion
106
is removed by polishing, the inside of the seam portion
106
is exposed upward. And the size of the seam portion
106
increases when hydrogen peroxide (aqueous solution of H
2
O
2
) used in polishing permeates into the seam portion
106
. Therefore, a problem of decrease in the contact area of the tungsten film
105
with the overlying wiring has arisen.
FIGS. 8A and 8B
are plan views showing a decreased contact area of the tungsten film
105
with the overlying wiring, and shows the state where a metal wiring
110
consisting of, for example, aluminum on the tungsten film
105
has been formed from the state shown in FIG.
7
B. Here,
FIG. 8A
shows an example wherein the metal wiring
110
is formed so as to overlap with the seam portion
106
, and
FIG. 8B
shows another example wherein the metal wiring
110
is formed beyond the seam portion
106
. In
FIGS. 8A and 8B
, the hatched areas show the regions where the metal wiring
110
contacts with the tungsten film
105
.
As
FIG. 8A
shows, when the metal wiring
110
is formed so as to overlap with the seam portion
106
, the larger the size of the seam portion
106
, the smaller the contact area of the metal wiring
110
with the plug consisting of the tungsten film
105
. Thus, a problem that the decreased contact area of the metal wiring
110
with the tungsten film
105
lowers the reliability of semiconductor devices, such as EM resistance, has arisen.
Also, as
FIG. 8B
shows, when the metal wiring
110
is formed beyond the seam portion
106
, the seam portion
106
is completely exposed upward. Therefore, when an aluminum alloy, which is a material of the metal wiring
110
, is subjected to dry etching, side etch occurs on the side of the metal wiring
110
along the contours of the seam portion
106
. Thereby, a problem that the reliability of semiconductor devices, such as EM resistance, is deteriorated by decrease in the contact area, has arisen.
Furthermore, another problem that a wet solution permeates into the seam portion
106
corroding the plug has arisen when the tungsten film
105
is polished by CMP using hydrogen peroxide, when the tungsten film
105
is cleaned after polishing, or when a polymer is removed during etching for forming the overlying metal wiring. Therefore, a problem of the deterioration of electrical properties of the plug has arisen.
In addition, when a tungsten plug is formed by polishing the tungsten film
105
using CMP, a problem of the deterioration of the accuracy of the alignment and superposition test marks for the photoengraving of the metal wirings, has arisen.
FIGS. 9A and 9B
are schematic sectional views showing the state where the accuracy of the alignment and superposition test marks has been deteriorated. Here,
FIG. 9A
shows the state immediately after the tungsten film
105
is formed, and
FIG. 9B
shows the state after polishing using CMP.
In
FIGS. 9A and 9B
, a tungsten film
105
is formed through a barrier metal film
111
in an opening
112
formed in an interlayer insulating film
102
. Here, the barrier metal film
111
is a laminated film of a titanium film
103
and a titanium nitride film
104
shown in
FIGS. 7A and 7B
. As
FIG. 9A
shows, since the tungsten film
105
is formed along the internal wall of the opening
112
, a step
105
a
is formed on the center of the opening
112
in the state after polishing shown in FIG.
9
B. The alignment and superposition for the photoengraving of the metal wirings is tested using this step
105
a.
However, since the tungsten film
105
on the bottom of the opening
112
of the interlayer insulating film
102
in the test mark portion is not completely removed by polishing using CMP, a problem that the step
105
a
becomes small has arisen.
Therefore, when a tungsten plug is formed using CMP, if the step
105
a
in the alignment and superposition test mark portion is formed together with the tungsten plug, the step
105
a
becomes shallow, and the detection of the step
105
a
in test becomes difficult. Therefore, a problem that the accuracy of alignment and superposition detection is lower than in the case of using the etch-back method, has arisen.
SUMMARY OF THE INVENTION
The present invention aims at the solution of the above-described problems, and the object of the present invention is to improve the electrical properties and reliability of plugs in semiconductor devices, and to achieve the improvement of t
Kamoshima Takao
Matsuoka Takeru
Yamashita Takashi
Hoang Quoc
Nelms David
Renesas Technology Corp.
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