Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-06-14
2003-11-11
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000
Reexamination Certificate
active
06645873
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods of manufacturing semiconductor devices and particularly relates to methods that involve selectively etching a sacrificial film, preferably a fluorine-containing silicon oxide film (hereinafter referred to as “SiOF”). Preferred embodiments relate to methods of forming a hollow structure that functions as an interlayer insulator by selectively etching a sacrificial film.
2. Description of the Related Art
In recent years, semiconductor devices have become faster and more highly integrated and resistance-capacitance (RC) coupling delays have become a large factor in signal processing time. RC delays can be decreased by reducing wiring capacitance. One way to do this is to use low dielectric constant materials such as fluorine-doped SiO
2
, porous SiO
2
, an organic film or a porous film, etc. However, these materials have not been put to practical use because of problems such as processing difficulty and insufficient heat-resistance, which can increase the complexity of the process and lower device reliability. In addition, the dielectric constant values of these materials are 3.4 to 3.8, which are not likely to be sufficient to meet the specifications of future semiconductor devices.
In the case of conventional techniques for obtaining a low dielectric constant by forming a hollow structure or a void using an SiO film, there is a problem that, if a via hole is opened without being aligned with an interconnection in a lower layer, the opening passes through the hollow and a material filling up the via hole flows into the hollow, causing a connection failure at the via hole. There is an additional problem that the height of the hollow increases and that the hollow is exposed during a process of polishing an interlayer insulator by CMP (Chemical Mechanical Polishing), causing an interconnection in an upper layer to break or to short-circuit.
As semiconductor devices have become more integrated, etching methods have been changing over from wet etching to vapor-phase etching in order to reduce contamination. Typically, vapor-phase etching involves two processes, removing an oxide film (typically applied as a pretreatment during a process such as covering a contact hole or forming a gate electrode film), then selectively etching one of several spontaneously formed oxides.
There is a technique for obtaining a low dielectric constant by creating a hollow between interconnections by selective etching. In the selective etching process, to obtain selectivity with a non-doped silicon oxidation film (hereinafter referred to as “NSG”), a phosphorus-doped oxidation film (hereinafter referred to as “PSG”) or a boronphosphorus-doped oxidation film (hereinafter referred to as “BPSG”), etc. is used. Selective etching, in principle, takes place by two chemical reactions shown as follows:
SiO
2
(P
2
O
5
)+4HF→SiF
4
+2H
2
O (I)
P
2
O
5
+3H
2
O→2H
9
PO
4
(II)
Reaction (I) takes place at an early stage when BPSG is etched by HF and reaction (II) is a phosphoric acid formation reaction which subsequently takes place. H
2
O formed by the chemical reaction (I) and P
2
O
5
contained in PSG or BPSG causes the chemical reaction (II), forming a phosphoric acid layer. Since HF is effectively ionized only in the phosphoric acid layer, PSG or BPSG is selectively etched. This method, however, has a problem: HF remains on a semiconductor substrate after etching because phosphoric acid formed by reaction (II) contains a small amount of HF and the vapor pressure is low. As a result, NSG is etched by absorbing moisture from the air when taking the semiconductor substrate out from a device. To prevent NSG from being etched, the semiconductor substrate is rinsed with pure water promptly after etching is completed. This, however, increases the number of steps and lowers process stability.
HF is much more selective in the absence of H
2
O. When water adheres onto other oxidation films or metal films exposed inside a reaction chamber, etching takes place by reacting with HF gas, resulting in lower etch selectivity. As a result, wire breakage or short-circuits in multilayer interconnections can occur, lowering yield. It has been reported that PSG formed on a thermal oxidation film can be selectively removed by controlling the moisture concentration in HF gas to be within the range of 0.1 ppm or less, see “Gas-phase Selective Etching of Native Oxide” published in Transaction on Electron Device, Vol. 37, No.1 (1990). However, lower process stability and higher costs are likely because of the difficulty of supplying HF with a low H
2
O content and in order to remove moisture formed by the etching reaction and adhering to an inner wall of the etching chamber.
SUMMARY OF THE INVENTION
This invention provides a method of processing a semiconductor substrate, which involves selective etching, without etching NSG and using a spontaneously oxidized film with high selectivity. This invention also provides a method of processing a semiconductor substrate, which performs selective etching without increasing the number of processes, while maintaining high process stability. Furthermore, this invention also provides a method of processing a semiconductor substrate, which can remove a spontaneous oxidation film and carry out selective etching in one device. Thus, a preferred embodiment provides a method of processing a semiconductor substrate, comprising: providing a semiconductor substrate disposed within a chamber, wherein the semiconductor substrate comprises a SiOF film and at least one other film, and selectively etching the SiOF film with a gas comprising HF.
This invention also provides a method of producing a hollow structure in a semiconductor device, forming an interlayer insulator with a dielectric constant approaching one, by performing selective etching using an oxidation film with high selectivity. This invention also provides a method of producing a hollow structure in a semiconductor device while maintaining high process stability by performing selective etching without leaving a residue and without increasing the number of processes. This invention also provides a selective etching method which brings about high selectivity by controlling the moisture concentration inside a reaction chamber. Thus, a preferred embodiment provides a method of producing a hollow structure in a semiconductor device, comprising: forming a first SiOF layer on a first interconnection; forming a first cap layer on the first SiOF layer; forming a first contact hole passing through the first cap layer and the first SiOF layer; forming a first contact plug by filling the first contact hole; and selectively etching the first SiOF layer to form a hollow structure.
REFERENCES:
patent: 5174855 (1992-12-01), Tanaka
patent: 5489553 (1996-02-01), Chen
patent: 5973371 (1999-10-01), Kasai
patent: 6103568 (2000-08-01), Fujiwara
patent: 6117763 (2000-09-01), May et al.
“Gas-phase Selective Etching of Native Oxide” published in IEEE Transaction on Electron Device, vol. 37, No. 1 pp. 107-115 (1990).
Ozaki Fumitoshi
Shimizu Akira
ASM Japan K.K.
Chen Kin-Chan
Knobbe Martens Olson & Bear LLP
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