Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-06-29
2003-07-29
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S720000, C438S725000
Reexamination Certificate
active
06599841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a manufacture of a semiconductor device, and in particular to a method of manufacturing a semiconductor device with a multilayer interconnection structure.
In microfabrication of a semiconductor integrated circuit device, the semiconductor industry has utilized wiring patterns and interlayer insulating films provided alternately, that is, a multilayer interconnection structure, to interconnect a large number of semiconductor devices formed on a common substrate. In the multilayer interconnection structure, an interlayer insulating film has been formed to cover a wiring pattern and a wiring pattern, in turn, has also been formed to cover the interlayer insulating film. Furthermore, a contact hole has been provided in such an interlayer insulating film, and the wiring pattern has been formed to contact a conductive plug which fills the contact hole.
Whereas the wiring patterns are typically formed of aluminum or an aluminum alloy in the conventional multilayer interconnection structure, the wiring patterns in the recent supermicrofabrication of the semiconductor integrated circuit device are formed of tungsten (W), which has a low resistivity equivalent to aluminum, in order to avoid problems of electromigration and hillock formation. Such a W pattern has also been used as a low-resistance gate electrode of a field-effect transistor.
2. Description of the Related Art
FIG. 1
shows a structure of a typical semiconductor device
10
with a conventional multilayer interconnection structure. Referring to
FIG. 1
, a field oxide film
11
a
is formed on a silicon substrate
11
to define an active region, wherein a gate electrode
12
carrying sidewall insulating films
12
a
and
12
b
at both sidewalls thereof is formed, with a gate oxide film not shown interposed between the substrate
11
and the gate electrode
12
. A channel region
11
d
is formed in the silicon substrate
11
in correspondence to the gate electrode
12
, and diffusion regions
11
b
and
11
c
are also formed at both sides of the channel region
11
d
in the silicon substrate
11
. An interlayer insulating film
13
is applied to cover the silicon substrate
11
in the semiconductor device
10
of
FIG. 1
, and a contact hole is then formed in the interlayer insulating film
13
so as to expose the diffusion region
11
b.
A W plug
14
is formed in the contact hole
13
A with a thin conductive film
14
a
with a structure provided by a TiN/Ti stacked layer interposed between the contact hole
13
A and the W plug
14
. The TiN/Ti conductive film
14
a
which has a structure of a TiN film deposited on a Ti film can be patterned on the interlayer insulating film
13
according to a desired conducting pattern. Furthermore, a W pattern
15
is applied to cover the conducting film pattern
14
a
on the interlayer insulating film
13
in accordance with a shape of the conducting film pattern
14
a.
Actually, the W plug
14
can be deposited by the steps of deposition by a chemical vapor deposition (CVD) method, followed by a chemical mechanical polishing (CMP) method. The W plug
14
has a seam
14
b
which is formed when the deposition of the W is performed to fill the contact hole
13
A. The W pattern
15
is covered with a conducting film
15
a
which has the same TiN/Ti stacked layer structure as the conducting film
14
a,
and the W pattern
15
is then covered with another interlayer insulating film
17
together with the conductive film
15
a
thereon. Then, a contact hole
17
A is formed in the interlayer insulating film
17
, by which the W pattern
15
, more accurately, the conducting film
15
a
on the W pattern
15
, is exposed. A thin conductive film
18
a
having the same TiN/Ti structure as the conductive film
14
a
or
15
a
is formed on the interlayer insulating film
17
to include the contact hole
17
A. The contact hole
17
A is filled with a W plug
18
with the conducting film
18
a
interposed between the contact hole
17
A and the W plug
18
. The W plug
18
also involves the same seam
18
b
as the seam
14
b.
By the way, recent very advanced microfabrication, that is, the manufacture of a semiconductor device offering sub-micron line widths, has provided a decreased size of the contact hole
13
A or
17
A by so-called induced enhancement of an aspect ratio thereof. In such a contact hole having the high aspect ratio, the TiN/Ti film
14
a
or
18
a
originally have a thickness of only a few nanometers. A thickness ratio of the TiN/Ti film to the W plug increases due to an inability to further decrease the TiN/Ti film thickness.
When the inventors of the present invention carried out an experiment of patterning by dry etching on a stacked conducting structure having a relatively thicker TiN/Ti film as compared to a W film thickness, it was discovered in this structure that aftercorrosion, in which Ti dissolves from the TiN/Ti film after the process of the dry etching, takes place.
FIG. 2
shows a structure of a sample
20
used in a preliminary experiment which forms the basis of the present invention. Referring to
FIG. 2
, the sample
20
was provided on a PSG film
22
covering a silicon substrate
21
. The sample
20
comprised a conductive film
23
having the TiN/Ti structure provided on the PSG film
22
, a W film
24
formed on the conductive film
23
, and an antireflection coating (ARC)
25
comprising SiON or an amorphous carbon provided on the W film
24
. A resist pattern
26
was formed on the ARC
25
. In the above experiment, the ARC
25
and the W film
24
under the ARC
25
were dry-etched as usual in a reaction chamber of a dry etching apparatus using the resist pattern as a mask and an etching gas containing F. The TiN/Ti film
23
under the W film was then dry-etched in the same reaction chamber using an etching gas including Cl. In addition, the resist pattern
26
, after the etching of the TiN/Ti film
23
, was removed by oxidation in an ashing apparatus. Deposition products including rabbit ears and the like remaining on the sidewalls of the resulting pattern were then dissolved and removed by an alkaline solution in a wet etching apparatus. However, it was discovered that the resulting conductive pattern was subjected to aftercorrosion, as shown in SEM photographs of
FIGS. 3A and 3B
indicated by a white circle, when the pattern was allowed to stand in the air. It is known with reference to a sectional SEM photograph in
FIG. 3C
that a portion subjected to aftercorrosion corresponds to the TiN/Ti film. If the wiring pattern in a multilevel interconnection structure is sujected to aftercorrosion, reliability of the overall semiconductor device will be reduced.
Specifically, the results of
FIGS. 3A-3C
were obtained from a sample having a TiN/Ti film
23
thickness of 100 (40/60) nanometers, a W film
24
thickness of 100 nanometers, and an ARC
25
comprising SiON with a film thickness of 32 nanometers. The ARC
25
and the W film
24
under the ARC
25
were dry-etched by a method of reactive ion etching (RIE) using a mixture gas of NF
3
and Ar as the etching gas in the reaction chamber of a parallel-plate dry etching apparatus. The TiN/Ti film
23
under the W film was then dry-etched using Cl
2
as the etching gas in the same reaction chamber. In the above experiment, after the dry etching of the TiN/Ti film
23
, the resist pattern was removed by an ashing process using an ultraviolet radiation excited oxygen plasma (UVEO plasma) in the same reaction chamber. The resulting structure was transferred to the wet etching apparatus, and the remaining deposition products, such as the rabbit ears and the like, were removed by an alkaline developing solution based on amines. In other words, in this experiment, after the ashing process of the resist pattern
26
, the conductive pattern was exposed to the air during the transfer stage from the dry etching apparatus to the wet etching apparatus.
FIGS. 3A-3C
show the resulting conductive pattern which was subjected to
Armstrong Westerman & Hattori, LLP
Kunemund Robert
Umez-Eronini Lynette T.
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